For a specific FPGA size, pins name is only a matter of package,
internally physical pads are the same: a unique bitstream per size is
necessary. This also simplify build.py by removing complexity to
extract model, size and package.
- a dict is added with supported packages per size
- only one bitstream is produces for artix/spartan7 size, package+size bitstreams are only symlinks.
- constraints files are also updated with BSCANE2/DRCK clocks constraints
- the gz is produces by build.py instead of by the Makefile
- all possibles bitstreams for XC7A/XC7S are now present.
Add board definition and FPGA part ID for the MILIANKE S200 EG4D20
development board. Also update related documentation and outdated URL.
Tested ok by loading bitstream to SRAM and FLASH.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
ANLOGICCABLE_VIDv1 should keep the old ANLOGICCABLE_VID to compatible
with the original device.
Fixes: 4b008a0 ("anlogicCable: refresh with new VID")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Programming to SRAM works. Programming flash works with a renamed
spiOverJtag bitfile - cs(g)484 is different from fg(g)484, but the
configuration flash IOs all end up on the same pads in the end.
- esp_usb_jtag: added xfer method to handle/simplify libusb_bulk_transfer calls
- src/esp_usb_jtag.cpp: simplify some operations
- src/esp_usb_jtag.cpp: writeTDI: fixed rx buffer index, added a basic code to handle end transaction
- src/esp_usb_jtag.cpp: writeTMS: store and uses _tdi & _tms
- src/esp_usb_jtag.cpp: toggleClock: re-uses _tdi/_tms
- src/esp_usb_jtag.cpp: writeTDI: ditto
- esp_usb_jtag: fixed verbosity level/be more quiet
- esp_usb_jtag: fixed writeTDI with end and tms transition: now integrated instead of distinct sequence. Fixed TDI value with tms transition. Working with ECP5
- esp_usb_jtag: added optional parameter to lower timeout error (useful when it's time to flush the device)
- esp_usb_jtag: fixed writeTDI when tx is NULL
- copy dirtyjtag to esp_usb_jtag, it compiles
- copy protocol definiton, defines and private data/struct from openocd esp_usb_jtag.c
- ulx3s_esp board with esp32s3 cable
- esp_usb_jtag specify usb vid:pid in jtag.cpp
- hardcode usb interface and endpoints
- getting caps
- set chip id (not applicable for fpga)
- tms write done, untested
- cleanup and toggle clk
- 32bit counting
- setting divisor (todo read base freq)
- div range within 1-255
- base speed from descriptor
- fix doc typo with swapped tms/tdi some cleanup but it doesn't work.
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Cyao
Junhui Liu
Julio Nunes Avelar
Tomserv-512
Dusk
Mike Goelzer
Bastian Löher
Emard
Nate White
Neo