Merge pull request #437 from UweBonnes/xc6v

Add spilOverJtag for Virtex6

doc/FPGAs.yml

@@ -235,6 +235,13 @@ Xilinx:
     Memory: OK
     Flash: NA
 
+  - Description: Virtex 6
+    Model:
+      - xc6vlx130t
+    URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-6.html
+    Memory: OK
+    Flash: OK
+
   - Description: Virtex UltraScale+
     Model:
       - xcvu9p

doc/boards.yml

@@ -797,6 +797,13 @@
   Memory: NA
   Flash: OK
 
+- ID: vec_v6
+  Description: Xilinx VCU118
+  URL: https://vmm-srs.docs.cern.ch/
+  FPGA: xc6vlx130tff784
+  Memory: OK
+  Flash: OK
+
 - ID: vcu118
   Description: Xilinx VCU118
   URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html
@@ -904,3 +911,10 @@
   FPGA: zynq7000 xc7z020clg400
   Memory: OK
   Flash: NA
+
+- ID: VMM3
+  Description: CERN board with VMM3
+  URL: https://vmm-srs.docs.cern.ch/
+  FPGA: xc7s50csga324?
+  Memory: OK
+  Flash: OK

spiOverJtag/Makefile

@@ -2,6 +2,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc6slx9tqg144 xc6slx9csg324 \
 	xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
 	xc6slx150tfgg484 xc6slx150tcsg484 \
+	xc6vlx130tff784 \
 	xc7a15tcpg236 \
 	xc7a25tcpg238 xc7a25tcsg325 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \

spiOverJtag/build.py

@@ -55,6 +55,10 @@ elif subpart == "xc3s":
     family = "Spartan3E"
     tool = "ise"
     speed = -4
+elif subpart == "xc6v":
+    family = "Virtex6"
+    tool = "ise"
+    speed = -1
 elif subpart in ["xcvu", "xcku"]:
     family = "Xilinx UltraScale"
     tool = "vivado"
@@ -72,7 +76,8 @@ if tool in ["ise", "vivado"]:
         "xc6slx45csg324"   : "xc6s_csg324",
         "xc6slx100fgg484"  : "xc6s_fgg484",
         "xc6slx150tcsg484" : "xc6s_csg484",
-        "xc6slx150tfgg484" : "xc6s_fgg484",
+        "xc6slx150tfgg484" : "xc6s_t_fgg484",
+        "xc6vlx130tff784"  : "xc6v_ff784",
         "xc7a15tcpg236"    : "xc7a_cpg236",
         "xc7a25tcpg238"    : "xc7a_cpg238",
         "xc7a25tcsg325"    : "xc7a_csg325",
@@ -116,6 +121,7 @@ if tool in ["ise", "vivado"]:
                             "xc6slx100fgg484":  "xc6slx100",
                             "xc6slx150tcsg484": "xc6slx150t",
                             "xc6slx150tfgg484": "xc6slx150t",
+                            "xc6vlx130tff784":  "xc6vlx130t",
                             "xc7k325tffg676":   "xc7k325t",
                             "xc7k325tffg900":   "xc7k325t",
                             "xc7k420tffg901":   "xc7k420t",
@@ -127,9 +133,10 @@ if tool in ["ise", "vivado"]:
                             "xc6slx16ftg256":   "ftg256",
                             "xc6slx16csg324":   "csg324",
                             "xc6slx45csg324":   "csg324",
-                            "xc6slx100fgg484":  "fgg384",
+                            "xc6slx100fgg484":  "fgg484",
                             "xc6slx150tcsg484": "csg484",
                             "xc6slx150tfgg484": "fgg484",
+                            "xc6vlx130tff784":  "ff784",
                             "xc7k325tffg676":   "ffg676",
                             "xc7k325tffg900":   "ffg900",
                             "xc7k420tffg901":   "ffg901",

spiOverJtag/constr_xc6s_fgg484.ucf

@@ -2,7 +2,7 @@ CONFIG VCCAUX = "2.5";
 
 NET "sdi_dq0"  LOC = AB20 | IOSTANDARD = LVCMOS25;
 NET "sdo_dq1"  LOC = AA20 | IOSTANDARD = LVCMOS25;
-NET "wpn_dq2"  LOC = R13  | IOSTANDARD = LVCMOS25;
+NET "wpn_dq2"  LOC = U14  | IOSTANDARD = LVCMOS25;
-NET "hldn_dq3" LOC = T14  | IOSTANDARD = LVCMOS25;
+NET "hldn_dq3" LOC = U13  | IOSTANDARD = LVCMOS25;
-NET "csn"      LOC = AA3  | IOSTANDARD = LVCMOS25;
+NET "csn"      LOC = T5   | IOSTANDARD = LVCMOS25;
-NET "sck"      LOC = Y20  | IOSTANDARD = LVCMOS25;
+NET "sck"      LOC = Y21  | IOSTANDARD = LVCMOS25;

spiOverJtag/constr_xc6s_t_fgg484.ucf

@@ -0,0 +1,8 @@
+CONFIG VCCAUX = "2.5";
+
+NET "sdi_dq0"  LOC = AB20 | IOSTANDARD = LVCMOS25;
+NET "sdo_dq1"  LOC = AA20 | IOSTANDARD = LVCMOS25;
+NET "wpn_dq2"  LOC = R13  | IOSTANDARD = LVCMOS25;
+NET "hldn_dq3" LOC = T14  | IOSTANDARD = LVCMOS25;
+NET "csn"      LOC = AA3  | IOSTANDARD = LVCMOS25;
+NET "sck"      LOC = Y20  | IOSTANDARD = LVCMOS25;

spiOverJtag/constr_xc6s_tqg144.ucf

@@ -0,0 +1,8 @@
+CONFIG VCCAUX = "2.5";
+
+NET "sdi_dq0"  LOC = P64 | IOSTANDARD = LVCMOS33;
+NET "sdo_dq1"  LOC = P65 | IOSTANDARD = LVCMOS33;
+NET "wpn_dq2"  LOC = P62 | IOSTANDARD = LVCMOS33;
+NET "hldn_dq3" LOC = P61 | IOSTANDARD = LVCMOS33;
+NET "csn"      LOC = P38 | IOSTANDARD = LVCMOS33;
+NET "sck"      LOC = P70 | IOSTANDARD = LVCMOS33;

spiOverJtag/constr_xc6v_ff784.ucf

@@ -0,0 +1,2 @@
+NET "sdi_dq0"  LOC = AF24 | IOSTANDARD = LVCMOS25;
+NET "csn"      LOC = AE24 | IOSTANDARD = LVCMOS25;

spiOverJtag/constr_xc7k_fbg676.xdc

@@ -0,0 +1,10 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+
+set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
+set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
+set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+

spiOverJtag/xc6/.gitignore

@@ -1,5 +0,0 @@
-*
-!*.gitignore
-!*.ucf
-!*.vhd
-!*.tcl

spiOverJtag/xc6/constr_xc6s_fgg484.ucf

@@ -1,6 +0,0 @@
-CONFIG VCCAUX = "2.5";
-
-NET "sdo" LOC = AA20 | IOSTANDARD = LVCMOS33;
-NET "sdi" LOC = AB20 | IOSTANDARD = LVCMOS33;
-NET "csn" LOC = T5   | IOSTANDARD = LVCMOS33;
-NET "sck" LOC = Y21  | IOSTANDARD = LVCMOS33;

spiOverJtag/xc6/constr_xc6slx9_tqg144.ucf

@@ -1,6 +0,0 @@
-CONFIG VCCAUX = "2.5";
-
-NET "sdo" LOC = P65 | IOSTANDARD = LVCMOS33;
-NET "sdi" LOC = P64 | IOSTANDARD = LVCMOS33;
-NET "csn" LOC = P38 | IOSTANDARD = LVCMOS33;
-NET "sck" LOC = P70 | IOSTANDARD = LVCMOS33;

spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl

@@ -1,44 +0,0 @@
-# 
-# Project automation script for spiOverJtag_xc6
-# 
-# Created for ISE version 14.7
-# 
-
-set myProject "xilinx_spiOverJtag_xc6"
-set myScript "xilinx_spiOverJtag_xc6.tcl"
-
-puts "\n$myScript: Rebuilding ($myProject)...\n"
-
-if { [file exists "${myProject}.xise" ] } {
-   project open $myProject
-} else {
-   project new $myProject
-
-   project set family "Spartan6"
-   project set device "xc6slx100"
-   project set package "fgg484"
-   project set speed "-2"
-   project set top_level_module_type "HDL"
-   project set synthesis_tool "XST (VHDL/Verilog)"
-   project set simulator "ISim (VHDL/Verilog)"
-   project set "Preferred Language" "VHDL"
-   project set "Enable Message Filtering" "false"
-   
-   project set "VHDL Source Analysis Standard" "VHDL-200X"
-   project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
-   
-   xfile add "constr_xc6s_fgg484.ucf"
-   xfile add "xilinx_spiOverJtag_xc6.vhd"
-   
-   project set top "bhv" "xilinx_spiOverJtag"
-}
-
-if { ! [ process run "Implement Design" ] } {
-   return false;
-}
-if { ! [ process run "Generate Programming File" ] } {
-   return false;
-}
-
-puts "Run completed successfully."
-project close

spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd

@@ -1,68 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity xilinx_spiOverJtag is
-	port (
-	 csn       : out std_logic;
-	 sdi       : out std_logic;
-	 sdo       : in std_logic;
-	 sck       : out std_logic;
-	 wpn	   : out std_logic;
-	 hldn      : out std_logic
-	);
-end entity xilinx_spiOverJtag;
-
-architecture bhv of xilinx_spiOverJtag is
-	signal capture, drck, sel, shift, update : std_logic;
-	signal runtest : std_logic;
-	signal tdi, tdo   : std_logic;
-	signal fsm_csn : std_logic;
-
-	signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
-begin
-	wpn <= '1';
-	hldn <= '1';
-	-- jtag -> spi flash
-	csn <= fsm_csn;
-	sdi <= tdi;
-	tdo <= tdi when (sel) = '0' else sdo;
-	sck <= drck;
-
-	tmp_cap_s <= capture and sel;
-	tmp_up_s <= update and sel;
-
-	process(drck, runtest) begin
-		if runtest = '1' then
-			fsm_csn <= '1';
-		elsif rising_edge(drck) then
-			if tmp_cap_s = '1' then
-				fsm_csn <= '0';
-			elsif tmp_up_s = '1' then
-				fsm_csn <= '1';
-			else
-				fsm_csn <= fsm_csn;
-			end if;
-		end if;
-	end process;
-
-	BSCAN_SPARTAN6_inst : BSCAN_SPARTAN6
-   generic map (
-      JTAG_CHAIN => 1  -- Value for USER command. Possible values: (1,2,3 or 4).
-   )
-   port map (
-      CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller.
-      DRCK => drck,       -- 1-bit output: Data register output for USER functions.
-      RUNTEST => runtest, -- 1-bit output: Output signal that gets asserted when TAP controller is in Run Test
-                          -- Idle state.
-
-      SEL => sel,         -- 1-bit output: USER active output.
-      SHIFT => shift,     -- 1-bit output: SHIFT output from TAP controller.
-      TDI => tdi,         -- 1-bit output: TDI output from TAP controller.
-      UPDATE => update,   -- 1-bit output: UPDATE output from TAP controller
-      TDO => tdo          -- 1-bit input: Data input for USER function.
-   );
-
-end architecture bhv;

spiOverJtag/xilinx_spiOverJtag.v

@@ -1,19 +1,31 @@
 module spiOverJtag
 (
-`ifndef xilinxultrascale
-	output csn,
-
 `ifdef spartan6
 	output sck,
-`endif
+	output csn,
-`ifdef spartan3e
-	output sck,
-`endif
 	output sdi_dq0,
 	input  sdo_dq1,
 	output wpn_dq2,
 	output hldn_dq3
-`endif // xilinxultrascale
+`define QSPI
+`elsif spartan3e
+	output sck,
+	output csn,
+	output sdi_dq0,
+	input  sdo_dq1
+`elsif virtex6
+	output csn,
+	output sdi_dq0
+`elsif xilinxultrascale
+`else
+ // Xilinx 7 but not ultrascale
+	output csn,
+	output sdi_dq0,
+	input  sdo_dq1,
+	output wpn_dq2,
+	output hldn_dq3
+`define QSPI
+`endif
 
 `ifdef secondaryflash
 	output sdi_sec_dq0,
@@ -29,11 +41,18 @@ module spiOverJtag
 	wire tdi;
 	reg fsm_csn;
 
-	assign wpn_dq2  = 1'b1;
+`ifdef QSPI
-	assign hldn_dq3 = 1'b1;
+        assign wpn_dq2  = 1'b1;
+        assign hldn_dq3 = 1'b1;
+`endif
 	// jtag -> spi flash
 	assign sdi_dq0 = tdi;
+`ifdef virtex6
+	wire di;
+	wire tdo = (sel) ? di : tdi;
+`else
 	wire tdo = (sel) ? sdo_dq1 : tdi;
+`endif
 	assign  csn = fsm_csn;
 
 	wire tmp_cap_s = capture && sel;
@@ -53,23 +72,13 @@ module spiOverJtag
 		end
 	end
 
-`ifdef spartan6
-	assign sck = drck;
-`else // !spartan6
-`ifdef spartan3e
-	assign sck = drck;
-	assign runtest = tmp_up_s;
-`else // !spartan6 && !spartan3e
 `ifdef xilinxultrascale
 	wire [3:0] di;
+	assign wpn_dq2  = 1'b1;
+	assign hldn_dq3 = 1'b1;
 	assign sdo_dq1 = di[1];
 	wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
 	wire [3:0] dts = 4'b0010;
-	// secondary BSCANE3 signals
-	wire sel_sec, drck_sec;
-
-	wire sck = (sel_sec) ? drck_sec : drck;
-
 	STARTUPE3 #(
 		.PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
 		.SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency (ns) for simulation.
@@ -92,7 +101,32 @@ module spiOverJtag
 		.USRDONEO (1'b1), // 1-bit input: User DONE pin output control.
 		.USRDONETS(1'b1)  // 1-bit input: User DONE 3-state enable output.
 	);
-`else // !spartan6 && !spartan3e && !xilinxultrascale
+`elsif  spartan3e
+	assign sck = drck;
+	assign runtest = tmp_up_s;
+`elsif spartan6
+	assign sck = drck;
+`elsif virtex6
+	STARTUP_VIRTEX6 #(
+		.PROG_USR("FALSE")
+	) startup_virtex6_inst (
+		.CFGCLK(),        // unused
+		.CFGMCLK(),       // unused
+		.CLK(1'b0),       // unused
+		.DINSPI(di),      // data from SPI flash
+		.EOS(),
+		.GSR(1'b0),       // unused
+		.GTS(1'b0),       // unused
+		.KEYCLEARB(1'b0),  // not used
+		.PACK(1'b1),      // tied low for 'safe' operations
+		.PREQ(),          // unused
+		.TCKSPI(),        // echo of CCLK from TCK pin
+		.USRCCLKO (drck), // user FPGA -> CCLK pin
+		.USRCCLKTS(1'b0), // drive CCLK not in high-Z
+		.USRDONEO (1'b1), // why both USRDONE are high?
+		.USRDONETS(1'b1)  // ??
+	);
+`else
 	STARTUPE2 #(
 		.PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
 		.SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.
@@ -112,8 +146,6 @@ module spiOverJtag
 		.USRDONETS(1'b1)  // 1-bit input: User DONE 3-state enable output
 	);
 `endif
-`endif
-`endif
 
 `ifdef spartan3e
 	BSCAN_SPARTAN3 bscane2_inst (
@@ -134,7 +166,9 @@ module spiOverJtag
 		.TDO2   ()         // 1-bit input: USER2 function
 	);
 `else
-`ifdef spartan6
+`ifdef virtex6
+	BSCAN_VIRTEX6 #(
+`elsif spartan6
 	BSCAN_SPARTAN6 #(
 `else
 	BSCANE2 #(
@@ -165,6 +199,10 @@ module spiOverJtag
 `ifdef secondaryflash
 	reg fsm_csn_sec;
 	wire tdo_sec;
+	// secondary BSCANE3 signals
+	wire sel_sec, drck_sec;
+
+	wire sck = (sel_sec) ? drck_sec : drck;
 
 	assign wpn_sec_dq2  = 1'b1;
 	assign hldn_sec_dq3 = 1'b1;
@@ -211,9 +249,6 @@ module spiOverJtag
 		.TDO     (tdo_sec)     // 1-bit input: Test Data Output (TDO) input
 		                   //              for USER function.
 	);
-`else // secondaryflash
-	assign sel_sec = 1'b0;
-	assign drck_sec = 1'b0;
 `endif // secondaryflash
 
 endmodule

src/board.hpp

@@ -225,6 +225,7 @@ static std::map <std::string, target_board_t> board_list = {
 	DFU_BOARD("ulx3s_dfu",        "", "dfu", 0x1d50, 0x614b, 0),
 	JTAG_BOARD("usrpx300",        "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
 	JTAG_BOARD("usrpx310",        "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
+	JTAG_BOARD("vec_v6",          "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu118",          "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu128",          "xcvu37p-fsvh2892", "ft4232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu1525",         "xcvu9p-fsgd2104",  "ft4232", 0, 0, CABLE_MHZ(15)),
@@ -240,7 +241,8 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("zedboard",        "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_10",      "xc7z010clg400",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_20",      "xc7z020clg400",  "digilent", 0, 0, CABLE_DEFAULT),
-	JTAG_BOARD("mini_itx",        "xc7z100ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT)
+	JTAG_BOARD("mini_itx",        "xc7z100ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("vmm3",            "xc7s50csga324", "ft2232", 0, 0, CABLE_DEFAULT)
 };
 
 #endif

src/part.hpp

@@ -64,6 +64,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x037c4093, {"xilinx", "spartan7", "xc7s25",          6}},
 	{0x0362f093, {"xilinx", "spartan7", "xc7s50",          6}},
 
+	/* Xilinx Virtex6 */
+	{0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}},
+
 	/* Xilinx 7-Series / Artix7 */
 	{0x037c2093, {"xilinx", "artix a7 25t",  "xc7a25",  6}},
 	{0x0362D093, {"xilinx", "artix a7 35t",  "xc7a35",  6}},

src/spiFlashdb.hpp

@@ -86,6 +86,19 @@ static std::map <uint32_t, flash_t> flash_list = {
 		.bp_len = 3,
 		.bp_offset = {(1 << 2), (1 << 3), (1 << 4), 0}}
 	},
+	{0x016018, {
+		.manufacturer = "spansion",
+		.model = "S25FL128L",
+		.nr_sector = 256,
+		.sector_erase = true,
+		.subsector_erase = false,
+		.has_extended = true,
+		.tb_otp = false,
+		.tb_offset = (1 << 6),
+		.tb_register = STATR,
+		.bp_len = 4,
+		.bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}}
+	},
 	{0x016019, {
 		.manufacturer = "spansion",
 		.model = "S25FL256L",