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spiOverJtag/xilinx_spiOverJtag: Update code since Virtex Ultrascale has apparently been replaced with Xilinx Ultrascale.

This commit is contained in:
Florent Kermarrec 2023-10-12 17:59:57 +02:00
parent ec35f15a51
commit 7a637a1085
1 changed files with 4 additions and 4 deletions
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8
spiOverJtag/xilinx_spiOverJtag.v
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@ -1,6 +1,6 @@
module spiOverJtag module spiOverJtag
( (
`ifndef virtexultrascale `ifndef xilinxultrascale
output csn, output csn,
`ifdef spartan6 `ifdef spartan6
@ -13,7 +13,7 @@ module spiOverJtag
input sdo_dq1, input sdo_dq1,
output wpn_dq2, output wpn_dq2,
output hldn_dq3 output hldn_dq3
`endif // virtexultrascale `endif // xilinxultrascale
`ifdef secondaryflash `ifdef secondaryflash
output sdi_sec_dq0, output sdi_sec_dq0,
@ -60,7 +60,7 @@ module spiOverJtag
assign sck = drck; assign sck = drck;
assign runtest = tmp_up_s; assign runtest = tmp_up_s;
`else // !spartan6 && !spartan3e `else // !spartan6 && !spartan3e
`ifdef virtexultrascale `ifdef xilinxultrascale
wire [3:0] di; wire [3:0] di;
assign sdo_dq1 = di[1]; assign sdo_dq1 = di[1];
wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0}; wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
@ -92,7 +92,7 @@ module spiOverJtag
.USRDONEO (1'b1), // 1-bit input: User DONE pin output control. .USRDONEO (1'b1), // 1-bit input: User DONE pin output control.
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output. .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output.
); );
`else // !spartan6 && !spartan3e && !virtexultrascale `else // !spartan6 && !spartan3e && !xilinxultrascale
STARTUPE2 #( STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation. .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.