From 7a637a1085d291b541b0b5502ea9c4e71aeed2ee Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Oct 2023 17:59:57 +0200
Subject: [PATCH] spiOverJtag/xilinx_spiOverJtag: Update code since Virtex
 Ultrascale has apparently been replaced with Xilinx Ultrascale.

---
 spiOverJtag/xilinx_spiOverJtag.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v
index b94ceea..241e42e 100644
--- a/spiOverJtag/xilinx_spiOverJtag.v
+++ b/spiOverJtag/xilinx_spiOverJtag.v
@@ -1,6 +1,6 @@
 module spiOverJtag
 (
-`ifndef virtexultrascale
+`ifndef xilinxultrascale
 	output csn,
 
 `ifdef spartan6
@@ -13,7 +13,7 @@ module spiOverJtag
 	input  sdo_dq1,
 	output wpn_dq2,
 	output hldn_dq3
-`endif // virtexultrascale
+`endif // xilinxultrascale
 
 `ifdef secondaryflash
 	output sdi_sec_dq0,
@@ -60,7 +60,7 @@ module spiOverJtag
 	assign sck = drck;
 	assign runtest = tmp_up_s;
 `else // !spartan6 && !spartan3e
-`ifdef virtexultrascale
+`ifdef xilinxultrascale
 	wire [3:0] di;
 	assign sdo_dq1 = di[1];
 	wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
@@ -92,7 +92,7 @@ module spiOverJtag
 		.USRDONEO (1'b1), // 1-bit input: User DONE pin output control.
 		.USRDONETS(1'b1)  // 1-bit input: User DONE 3-state enable output.
 	);
-`else // !spartan6 && !spartan3e && !virtexultrascale
+`else // !spartan6 && !spartan3e && !xilinxultrascale
 	STARTUPE2 #(
 		.PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
 		.SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.