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xilinx: fpga model must be used for spiOverJtag bistream selection

This commit is contained in:
Gwenhael Goavec-Merou 2020-02-16 15:06:06 +01:00
parent 50c8d54791
commit 563e748c69
1 changed files with 1 additions and 1 deletions
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2
src/xilinx.cpp
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@ -81,7 +81,7 @@ void Xilinx::program_spi(unsigned int offset)
{ {
// DATA_DIR is defined at compile time. // DATA_DIR is defined at compile time.
std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_"; std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_";
bitname += fpga_list[idCode()].family + ".bit"; bitname += fpga_list[idCode()].model + ".bit";
/* first: load spi over jtag */ /* first: load spi over jtag */
BitParser bitfile(bitname, _verbose); BitParser bitfile(bitname, _verbose);