From 563e748c69eb17aa9ec452678cced5140b477d3d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sun, 16 Feb 2020 15:06:06 +0100 Subject: [PATCH] xilinx: fpga model must be used for spiOverJtag bistream selection --- src/xilinx.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/xilinx.cpp b/src/xilinx.cpp index cec8f1f..99521e5 100644 --- a/src/xilinx.cpp +++ b/src/xilinx.cpp @@ -81,7 +81,7 @@ void Xilinx::program_spi(unsigned int offset) { // DATA_DIR is defined at compile time. std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_"; - bitname += fpga_list[idCode()].family + ".bit"; + bitname += fpga_list[idCode()].model + ".bit"; /* first: load spi over jtag */ BitParser bitfile(bitname, _verbose);