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xilinx: fix a random segfault and add progress status for load in sram

This commit is contained in:
Gwenhael Goavec-Merou 2020-02-16 15:03:55 +01:00
parent 906507b3b5
commit 50c8d54791
1 changed files with 21 additions and 1 deletions
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22
src/xilinx.cpp
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@ -8,6 +8,7 @@
#include "xilinx.hpp"
#include "part.hpp"
#include "progressBar.hpp"
Xilinx::Xilinx(FtdiJtag *jtag, std::string filename, bool verbose):
Device(jtag, filename, verbose)
@ -153,7 +154,26 @@ void Xilinx::program_mem(BitParser &bitfile)
* EXIT1-DR.
*/
/* GGM: TODO */
_jtag->shiftDR(bitfile.getData(), NULL, 8*bitfile.getLength());
int byte_length = bitfile.getLength();
uint8_t *data = bitfile.getData();
int tx_len, tx_end;
int burst_len = byte_length / 100;
ProgressBar progress("Flash SRAM", byte_length, 50);
for (int i=0; i < byte_length; i+=burst_len) {
if (i + burst_len > byte_length) {
tx_len = (byte_length - i) * 8;
tx_end = 1;
} else {
tx_len = burst_len * 8;
tx_end = 0;
}
_jtag->read_write(data+i, NULL, tx_len, tx_end);
_jtag->flush();
progress.display(i);
}
progress.done();
/*
* 15: Enter UPDATE-DR state. X 1 1
*/