From 259914910f0aef917e91cc94b086704bf4237a49 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 10 Mar 2022 18:53:41 +0100 Subject: [PATCH] board: Xilinx ZC706 --- doc/boards.yml | 8 ++++++++ src/board.hpp | 1 + 2 files changed, 9 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index b970174..a4deaad 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -491,6 +491,14 @@ Memory: OK Flash: NA +- ID: zc706 + Description: Xilinx ZC706 + URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html + FPGA: zynq7000 xc7z045ffg900 + Memory: OK + Flash: NA + Constraints: ZC706 + - ID: zedboard Description: Avnet ZedBoard URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/ diff --git a/src/board.hpp b/src/board.hpp index dada6a8..2852f51 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -186,6 +186,7 @@ static std::map board_list = { SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232", DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT), JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zc706", "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT), JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT), };