diff --git a/doc/boards.yml b/doc/boards.yml
index 125b2c6..94897f8 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -76,6 +76,13 @@
   Memory: OK
   Flash: OK
 
+- ID: antmicro_lpddr4_tester
+  Description: Antmicro LPDDR4 Test Board
+  URL: https://opensource.antmicro.com/projects/lpddr4-test-board
+  FPGA: Kintex7 xc7k70t
+  Memory: OK
+  Flash: OK
+
 - ID: arty_a7_35t
   Description: Digilent Arty A7
   URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
diff --git a/src/board.hpp b/src/board.hpp
index a531c58..54fa83d 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -113,6 +113,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("alinx_ax7102",    "xc7a100tfgg484", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("antmicro_lpddr4_tester", "xc7k70tfbg484", "ft4232", 0, 0, CABLE_DEFAULT),
 	/* left for backward compatibility, use right name instead */
 	JTAG_BOARD("arty",            "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),
 	JTAG_BOARD("arty_a7_35t",     "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),