diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index def1063..09b234f 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -68,7 +68,9 @@ Intel: Flash: OK - Description: Cyclone IV CE - Model: EP4CE22 + Model: + - EP4CE22 + - EP4CE115 URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html Memory: OK Flash: OK diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 3d091a6..93cef95 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -10,7 +10,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6sl xc7k420tffg901 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) -ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 5ce223 5ce423 5ce523 5ce927 +ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS))) BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES) diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index 12ac40e..90076eb 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -121,6 +121,7 @@ if tool in ["ise", "vivado"]: else: full_part = { "10cl025256": "10CL025YU256C8G", + "ep4ce11523": "EP4CE115F23C7", "ep4ce2217" : "EP4CE22F17C6", "ep4ce1523" : "EP4CE15F23C8", "5ce223" : "5CEFA2F23I7", diff --git a/spiOverJtag/spiOverJtag_ep4ce11523.rbf.gz b/spiOverJtag/spiOverJtag_ep4ce11523.rbf.gz new file mode 100644 index 0000000..ad552d2 Binary files /dev/null and b/spiOverJtag/spiOverJtag_ep4ce11523.rbf.gz differ diff --git a/src/part.hpp b/src/part.hpp index a4a7973..5d26059 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -79,6 +79,7 @@ static std::map fpga_list = { {0x04730093, {"xilinx", "zynqmp", "xczu7ev", 6}}, {0x020f20dd, {"altera", "cyclone III/IV", "EP3C16/EP4CE15", 10}}, + {0x020f70dd, {"altera", "cyclone IV", "EP4CE115", 10}}, {0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},