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ngspice/examples/xspice/verilator
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Giles Atkinson 1244f4dc1f Add additional examples of Verilog co-simulation and share the Verilog 
source and large parts of the example circuits between Verilator and
Icarus Verilog.  Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
 		2024-07-25 21:33:32 +02:00
..
555.cir Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
555.shared Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
555.v Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
README.txt Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
adc.cir Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
adc.shared Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
adc.v Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
delay.cir Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
delay.v Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
pwm.cir Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00
pwm.v Add additional examples of Verilog co-simulation and share the Verilog 2024-07-25 21:33:32 +02:00

README.txt 

The circuits in this directory illustrate the use of the d_cosim
XSPICE code model as a container for a Verilog simulation, using the
Verilator compiler. The example circuits are:

555.cir: The probably familiar NE555 oscillator provides a minimal example
of combined simulation with SPICE and Verilog.  The digital part of the IC,
a simple SR flip-flop, is expressed in Verilog.

delay.v: A very simple example of using delays in Verilog to generate
waveform outputs.

pwm.c: Verilog delays controlling a pulse-width modulated output generate
an approximate sine wave.

adc.cir: Slightly more complex Verilog describes the controlling part
of a switched-capacitor ADC.

Before a simulation can be run, the associated Verilog code must be compiled
by Verilator using a command script that is included with ngspice:

    ngspice vlnggen 555.v

That should create a shared library file, 555.so (or 555.DLL on Windows)
that will be loaded by the d_cosim code model.  The compiled Verilog code that
it contains will be executed during simulation.  Similar compilations
are needed to prepare the other examples, but for Verilog with delays the
command looks like:

    ngspice vlnggen -- --timing delay.v

(The "--" prevents "--timing" from being treated as a ngspice option, so it is
passed on to Verilator.)