Giles Atkinson 1244f4dc1f Add additional examples of Verilog co-simulation and share the Verilog ... source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2024-07-25 21:33:32 +02:00
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d_lut	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
d_process	Add notes on the structure and organization of an external d_process program.	2023-10-28 19:43:50 +02:00
d_source	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delay	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
delta-sigma	add y-axis label	2022-02-01 12:21:08 +01:00
filesource	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
icarus_verilog	Add additional examples of Verilog co-simulation and share the Verilog	2024-07-25 21:33:32 +02:00
original-examples	Add null-pointer checks to some code that crashed when trying	2023-11-09 12:07:31 +00:00
pll	Add an option to the iplot command: -d sets the number of simulation	2023-07-15 11:29:32 +02:00
pwm-osc	Examples for d_pwm and d_osc	2022-12-11 15:27:42 +01:00
state	Obtain memory and simulation time	2022-01-03 22:11:15 +01:00
table	New tables for MOS devices	2022-10-07 13:11:18 +02:00
various	Various filter examples using Laplace expression x_fer	2023-01-20 15:07:37 +01:00
verilator	Add additional examples of Verilog co-simulation and share the Verilog	2024-07-25 21:33:32 +02:00