2 Commits

Author	SHA1	Message	Date
Giles Atkinson	1244f4dc1f	Add additional examples of Verilog co-simulation and share the Verilog ... source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2024-07-25 21:33:32 +02:00
Giles Atkinson	c18447f9f5	Add the support files for co-simulation with Verilog code ... compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds.	2023-11-27 20:55:59 +00:00