Commit Graph

3668 Commits

Author SHA1 Message Date
Holger Vogt bcec3cb5e3 Updating links to ngspice web pages 2023-03-18 14:37:02 +01:00
Brian Taylor 4111aaf110 When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer. 2023-03-18 14:36:45 +01:00
Brian Taylor a6b2773c90 For a ugate timing model, when tphlXX/tplhXX is not found, set the fall/rise delay to zero (1.0e-12). 2023-03-18 14:36:35 +01:00
Brian Taylor 0e5a5a62ac 74F550 and 74F551 have only fall delays on the inverters. Use the fall delay for both rise and fall. 2023-03-18 14:36:23 +01:00
Brian Taylor 3a76a1ef52 Prepare for inertial_delay model parameter. 2023-03-18 14:36:17 +01:00
Brian Taylor 4b30113f60 Check current_subckt is set when printing TRANS_OUT. 2023-03-18 14:36:00 +01:00
Holger Vogt 8915d42241 Prevent crash during .probe p(...) when no subcircuits are given. 2023-03-18 14:35:33 +01:00
Holger Vogt 5ee7a0ad2d prevent crash when defect .model line is given
(no model name or no model type)
2023-03-18 14:35:11 +01:00
Holger Vogt d2fb3fb16b Prevent memory leak.
Remove use controls.
Safeguard against NULL.
2023-03-18 14:34:57 +01:00
Giles Atkinson 79fcb5d4bd Fix plotting bug reported by Robert Turnbull: ngspice-devel 2023-02-10. 2023-03-18 14:34:50 +01:00
Giles Atkinson 2233e2f825 Fix Bug #624 - "Destroy All Fails with an Open Plot Window" for X11.
Move XftDrawDestroy() call to a point where the window still exists.
2023-03-18 14:34:20 +01:00
Holger Vogt 75f9451702 Fix bug 624 also for MS Windows
by moving DestroyGraph() from WM_CLOSE to RemoveWindow()
2023-03-18 14:33:51 +01:00
Giles Atkinson d9b52eb3e1 Fix a bug reported by Thomas Hoffmann in ngspice-users discussion,
2023-02-18.  Incorrect tests were used to detect a crossing in the
first two data samples.
2023-03-18 14:33:13 +01:00
Giles Atkinson dbb5219dc7 Fix a crash reported by Thomas Hoffmann when using the "TARG AT=xxxx"
variant of "measure", General Form 1.
2023-03-18 14:32:46 +01:00
Brian Taylor 8dd16feee4 Use dstrings where fixed size char buffers should not have been used. 2023-03-18 14:32:31 +01:00
Brian Taylor 3365fd4309 Remove dead code. 2023-03-18 14:32:19 +01:00
Holger Vogt 50173ac617 Enable potential calls to tprint() for debugging 2023-03-18 14:32:04 +01:00
dwarning bccaee4821 correct fft dc scaling bug #620 2023-03-18 14:31:24 +01:00
Holger Vogt 9c6fe3f8e4 Definitely exclude A devices from power probing (and others with less than 2 pins). 2023-03-18 14:31:05 +01:00
Holger Vogt 5cb5d218c9 Remove the obsolete RETSIGTYPE, replace by void 2023-03-18 14:30:29 +01:00
Holger Vogt 3ff9643f49 Add a scale factor 'a' (atto, 1e-18) 2023-03-18 14:30:03 +01:00
Holger Vogt 4309bad14d Set the recounter to 0 upon every exit from function inp_get_param_level 2023-02-03 18:50:55 +01:00
Holger Vogt 33a3557910 Safeguard against NULL pointers 2023-02-03 11:44:57 +01:00
Holger Vogt 712ed8ac77 Safeguard against stack overflow, when wrongly introduce a circular
parameter dependency
2023-02-03 11:33:36 +01:00
Holger Vogt 20711c1c25 Safeguard against NULL pointers 2023-02-01 22:35:01 +01:00
Brian Taylor 56d0c72924 Add port directions when logicexp or pindly are present. 2023-02-01 17:39:37 +01:00
Brian Taylor 9c9301eca8 Remove delay ifdefs. 2023-02-01 17:38:28 +01:00
Brian Taylor f674b64264 Remove dead code from previous commit. 2023-02-01 17:37:36 +01:00
Brian Taylor f570b04d6c For unspecified gate delays (logic and tristate gates), which PSpice would consider as zero, set the rise and fall delays to 1.e-12s (the minimum for Xspice). For dff, jkff, dlatch, and srlatch use the Xspice default 1.0ns for rise and fall delays. If the ngspice variable (ps_port_directions & 2) is true, write the translated subckt to stdout, with TRANS_OUT prefix, for debugging purposes. The user could edit and replace the translated subckt if desired. 2023-02-01 17:36:36 +01:00
holger b3676bb763 enable make dist 2023-01-30 13:09:15 +01:00
Holger Vogt 4b8d575122 Add a user definable variable enable_noisy_r (for .spiceinit)
to enable noise calculation for all behavioral resistors.
May locally be switched off by instance parameter noisy=0
If enable_noisy_r is not set, noise simulation
may locally be enabled by instance parameter noisy=1.
2023-01-27 16:12:42 +01:00
Holger Vogt 49b7cb85db Add a shunt resistor of 1e15 Ohms to any X (subcircuit call) line
when the node name contain 'unconnected' and .probe alli is called.
2023-01-15 13:38:15 +01:00
Brian Taylor dcfe4e7134 ERROR messages should be printed to stderr. 2023-01-15 13:37:42 +01:00
Brian Taylor a76f8d5149 Fix some comments. 2023-01-09 16:33:25 +01:00
Holger Vogt ebd430e51b A preliminary fix to bug report 612
Don't set series voltage sources when flag probe_alli_nox
is set in .spiceinit
2023-01-09 16:32:00 +01:00
Holger Vogt 1a4880344f Update to fcn tprint:
allow multiple printouts in a single simulation run,
without overwriting the previous printout.
2023-01-09 16:31:44 +01:00
Holger Vogt 164ed05786 enable 'off', 'print', 'save' being part of a node name.
Only plain 'off' (case of bipolar), or 'print', 'save'
(in case of CIDER) will not be allowed.
2023-01-09 16:31:15 +01:00
Brian Taylor 6117836d01 Ensure that amatch output is not binary data. 2023-01-09 16:30:22 +01:00
Brian Taylor 90ec717f3b Add variable ps_udevice_exit. If set non-zero, ngspice will exit if there is an error processing f_logicexp or f_pindly. 2023-01-09 16:29:24 +01:00
Brian Taylor 5e6452099e Return errors from f_logicexp and f_pindly without calling exit. 2023-01-09 16:29:08 +01:00
Brian Taylor 0a3cdf8e3a Add more error checks for f_logicexp and f_pindly. 2023-01-09 16:28:43 +01:00
Giles Atkinson 301f50335d Add limited support for string-valued parameters in .param lines.
The right-hand side of an assignment may be a string expression
made up from quoted strings, and identifiers for other string parameters,
optionally in braces.  There may be no un-quoted spaces.
Example: .param str4=str1"String 4"str2{str3}

Subcircuits may have default and actual string parameters, but the values
must be single identifiers, not quoted strings or string expressions.
2023-01-09 16:26:59 +01:00
Brian Taylor fe52771aff Remove the old inverter code. 2022-12-27 14:21:05 +01:00
Brian Taylor 3578deda80 Refactor new_gen_output_models. 2022-12-27 14:20:43 +01:00
Holger Vogt 199b9deee6 For OSDI n devices: Enable model translation,
if model has been inside subcircuit.
2022-12-27 14:19:37 +01:00
Pascal Kuthe 79b2d2d520 removed unneded changes 2022-12-27 14:09:22 +01:00
Holger Vogt a4d13dae24 Suppress model type warning when device is of type N. 2022-12-27 14:04:56 +01:00
Holger Vogt 8f0eab90ee Replace 'a' by 'n' for OSDI device 2022-12-27 14:03:39 +01:00
Holger Vogt a95b114768 Revert previous commit: now treat a devices like ordinary devices. 2022-12-27 13:59:42 +01:00
Holger Vogt d8eb685fcc Preliminary fix to get_number_terminals:
check for tokens with '=' to stop and get number of nodes by
stepping back.
2022-12-27 13:59:20 +01:00
Holger Vogt 6ece9b5748 Exclude XSPICE specific error message.
Don't call fcn get_adevice_model_name().

Return a fixed value (5) for number of nodes:
This is wrong. It has to be replaced by a safe
method to figure out the number of terminals for
varying Verilog-A device models.
2022-12-27 13:57:20 +01:00
Holger Vogt 638ddbc91f Add case 'a' to fcn translate.
This is a hack, to be removed/altered when switching to
reference designator N instead of A.
2022-12-27 13:56:50 +01:00
Pascal Kuthe acfaf023b3 prototype for Verilog-A integration using OSDI and OpenVAF
This initial prototype is capable of performing DC, transient and AC
analysis. Not all features of OSDI are supported yet and there are still
some open questions regarding ngspice integration. However many usecase
already work very well and a large amount of CMC models are supported.
The biggest missing feature right now is noise analysis.

test: test case for diode DC working with SH

test: add transient analysis to osdi_diode test

test: added docu text to osdi_diode test

test: added test case directories

fix: bug in osdi_load

test: small change to netlist

fix: implement DEVunsetup

fix: correct behaviour for MODEINITSMSIG

test: osdi diode enable all analysis modes

removed netlist

ignoring test results

added the build of the diode shared object to the python test script

deleting old stuff and always rebuilding the shared object

added diode_va.c to the repo

preparing CI

Create .gitlab-ci.yml file

(testing) add res, cap and multiple devices test

feat: use osdi command to load files

Previously OSDI shared object files were loaded from fixed directories.
This was unreliable, inconvenient and caused conflicts with XSPICE.

This commit remove the old loading mechanism and instead introduces the
`osdi` command that can load (a list of) osdi object files (like the
codemodel command for XSPICE). A typical usecase will use this as a
precommand in the netlist:

.control
pre_osdi foo.osdi
.endc

If the specified file is a relative path it is first resolved relative
to the parent directory of the netlist. If the osdi command is invoked
from the interactive prompt the file is resolved relative to the current
working directory instead.

This commit also moves osdi from the devices folder to the root src
folder like xspice. This better reflects the role of the code as users
may otherthwise (mistakenly) assume that osdi is just another
handwritten model.

test: update tests to new command

fix: do not ignore first parameter

feat: implement log message callback

fix: don't generate ddt matrix/rhs in DC sweep

fix: missing linker script

update to osdi 0.3

(testing) simplify test cases, fix bug

(testing) multiple devices test improvement

(testig) node collapsing bugfix

test: increase tolerance in tests

feat: update to newest OSDI header

fix: temperature update dt behaviour

fix: ignored models

fix: compilation script

fix: allow hicum/l2 to compile with older c++ compilers

fix: set required compiler flags for osdi

fix: disable x by default

fix: add missing SPICE functions

fix: update diode to latest ngspice version

feat: implement python CMC test runner

doc: Add README_OSDI.md

fix: make testing script work with python version before 3.9

fix: free of undefined local variable

fix: do not calculate time derivative during tran op

update osdi version

fixes for compilation on windows
2022-12-27 13:51:57 +01:00
Brian Taylor 0805856fb7 Distinguish between set/reset delays when possible. 2022-12-19 12:43:00 +01:00
Brian Taylor 253df17949 Make it optional to use zl/zh/lz/hz delays for utgate. 2022-12-19 12:42:36 +01:00
Brian Taylor 4c457a3cd4 Avoid unnecessary calculations for utgate. 2022-12-19 12:42:06 +01:00
Brian Taylor a4b609fb6a For utgate timing models, if hl/lh are not present use zl/zh/lz/hz to give a more accurate tristate delay. 2022-12-19 12:41:18 +01:00
Brian Taylor 021982799e More conservative delay estimates for timing model type ugff. 2022-12-19 12:40:50 +01:00
Brian Taylor 11f6eace68 For dff/jkff, obtain more conservative estimates for clk_delay, set_delay and reset_delay. 2022-12-19 12:40:06 +01:00
Holger Vogt cc8b651562 re-enable making old app nutmeg 2022-12-11 15:47:22 +01:00
Brian Taylor 47260e2eb8 Rewrite extract_model_param. 2022-12-11 15:38:08 +01:00
Brian Taylor 0924fbb7eb Modify the delay calculation for non-conforming timing model in .subckt CD4572UB. 2022-12-11 15:37:34 +01:00
Holger Vogt a5eaac128a For monotonic plotting find out the majority of increasing or decreasing
x-axis values, add a warning to add 'retraceplot' to plot all if more than
10% of the values deviate from the majority.
2022-12-11 15:37:14 +01:00
Holger Vogt 9613625840 Prevent seg fault after strange input like
*no circuit
.save all
.probe alli
.op
.end
2022-12-11 15:36:22 +01:00
Pascal Kuthe 744002dc49 fix sigfault on older c compilers 2022-12-11 15:35:53 +01:00
Giles Atkinson 73e8fed0fc Fix warnings from gcc 10.2.1. 2022-12-11 15:35:14 +01:00
Brian Taylor 929d1f5190 Added xor/xnor for logicexp timing models. 2022-12-11 15:34:56 +01:00
Brian Taylor 7ff8f3773f Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 2022-12-11 15:34:33 +01:00
Holger Vogt e967b31c94 Add a new compatibility mode xs (for XSPICE) 2022-12-11 15:32:30 +01:00
Holger Vogt 27fb6cd0a6 Allow resetting the limit for warning mesaages, when a new run is started. 2022-12-11 15:32:11 +01:00
Brian Taylor 1511214874 Add more debug instrumentation. 2022-12-11 15:31:09 +01:00
Brian Taylor fe733a8ca2 Use tilde '~' inputs instead of creating inverters. 2022-12-11 15:30:41 +01:00
Holger Vogt 59e28ac2a2 Remove mentioning line number 0, which has been incomprehensible. 2022-12-11 15:30:12 +01:00
Holger Vogt 59413a7f71 Add error messages when controlled_exit is called:
No exit without message.
2022-12-11 15:29:47 +01:00
Holger Vogt d0f686727d Add new functions for operators x**y or x^y
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
2022-12-11 15:27:02 +01:00
Brian Taylor 9932a78e39 Add safety braces. 2022-12-11 15:26:42 +01:00
Brian Taylor 5726c9ff0b Tidy up debug tracing code. 2022-12-11 15:26:16 +01:00
Brian Taylor aa2f3b7bbb Fix memory leaks. 2022-12-11 15:25:52 +01:00
Brian Taylor 4294f49968 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented. 2022-12-11 15:25:24 +01:00
Brian Taylor cefa6b380c When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary. 2022-12-11 15:25:00 +01:00
Brian Taylor 029df5a3d6 Check that the bparse gen_tab optimization loop finishes when no more improvements occur. 2022-12-11 15:24:35 +01:00
Brian Taylor aff20b9db1 Remove asserts, replace fixed size lexer_buf. 2022-12-11 15:21:09 +01:00
Brian Taylor d54c1fc091 Add pindly tristate example. Cleanup error handling. 2022-12-11 15:20:27 +01:00
Brian Taylor 0627af435a Remove most asserts. 2022-12-11 15:20:03 +01:00
Brian Taylor b142be7fde Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE. 2022-12-11 15:19:39 +01:00
Brian Taylor 4e76586b6b Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly. 2022-12-11 15:19:17 +01:00
Brian Taylor 13c01abf0d Fix a typo, add more comments. 2022-12-11 15:18:52 +01:00
Brian Taylor 68f0d49f58 Add support for TRISTATE: in PINDLY. 2022-12-11 15:18:32 +01:00
Brian Taylor 363179ce2f Fix potential memory leak, clean out debug code. 2022-12-11 15:18:12 +01:00
Brian Taylor 499bef097e Better estimates of rise/fall delays in PINDLYs with outputs separated by CASE. 2022-12-11 15:17:51 +01:00
Brian Taylor a01edf2f36 Fix visualc compiler warnings. 2022-12-11 15:17:33 +01:00
Brian Taylor 22a3af8a1e Improve delay estimates for pindly output buffers. 2022-12-11 15:17:17 +01:00
Brian Taylor 64c2c1ee05 Initial handling of PINDLY. Output buffers without rise/fall delay estimates. 2022-12-11 15:16:57 +01:00
Brian Taylor 62aab3885d Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards. 2022-12-11 15:16:37 +01:00
Brian Taylor 7c699a599f Fix potential memory leak. 2022-12-11 15:16:20 +01:00
Brian Taylor a54aa4d1f7 Initial logicexp parser and gate generator. 2022-12-11 15:16:02 +01:00
Brian Taylor 4a904cdf18 Add drive 0/1 for $d_lo/$d_hi. 2022-12-11 15:15:44 +01:00
Holger Vogt 4b15632f9b Function ngSpice_Circ() may receive empty lines.
Skip these lines while setting the netlist.
2022-10-26 22:24:52 +02:00
Holger Vogt 97ee2d8047 Fix typo 2022-10-26 17:48:34 +02:00
Holger Vogt a6c28e44ff Add info on shared library 2022-10-24 17:04:45 +02:00