Brian Taylor
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8c69ada5b5
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The logicexp example in the PSpice ref. manual has a name with a '+' character (LCN+4). Update lexer_scan.
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2023-03-22 14:26:43 +01:00 |
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Brian Taylor
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40a540a2ff
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Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays.
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2023-03-22 14:26:18 +01:00 |
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Brian Taylor
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164db58404
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The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE.
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2023-03-22 14:25:51 +01:00 |
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Brian Taylor
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4111aaf110
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When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer.
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2023-03-18 14:36:45 +01:00 |
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Brian Taylor
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3a76a1ef52
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Prepare for inertial_delay model parameter.
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2023-03-18 14:36:17 +01:00 |
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Brian Taylor
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8dd16feee4
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Use dstrings where fixed size char buffers should not have been used.
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2023-03-18 14:32:31 +01:00 |
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Brian Taylor
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3365fd4309
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Remove dead code.
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2023-03-18 14:32:19 +01:00 |
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Brian Taylor
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56d0c72924
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Add port directions when logicexp or pindly are present.
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2023-02-01 17:39:37 +01:00 |
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Brian Taylor
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dcfe4e7134
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ERROR messages should be printed to stderr.
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2023-01-15 13:37:42 +01:00 |
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Brian Taylor
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a76f8d5149
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Fix some comments.
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2023-01-09 16:33:25 +01:00 |
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Brian Taylor
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6117836d01
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Ensure that amatch output is not binary data.
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2023-01-09 16:30:22 +01:00 |
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Brian Taylor
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5e6452099e
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Return errors from f_logicexp and f_pindly without calling exit.
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2023-01-09 16:29:08 +01:00 |
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Brian Taylor
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0a3cdf8e3a
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Add more error checks for f_logicexp and f_pindly.
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2023-01-09 16:28:43 +01:00 |
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Brian Taylor
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fe52771aff
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Remove the old inverter code.
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2022-12-27 14:21:05 +01:00 |
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Brian Taylor
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3578deda80
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Refactor new_gen_output_models.
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2022-12-27 14:20:43 +01:00 |
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Brian Taylor
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929d1f5190
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Added xor/xnor for logicexp timing models.
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2022-12-11 15:34:56 +01:00 |
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Brian Taylor
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7ff8f3773f
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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2022-12-11 15:34:33 +01:00 |
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Brian Taylor
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1511214874
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Add more debug instrumentation.
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2022-12-11 15:31:09 +01:00 |
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Brian Taylor
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fe733a8ca2
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Use tilde '~' inputs instead of creating inverters.
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2022-12-11 15:30:41 +01:00 |
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Brian Taylor
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9932a78e39
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Add safety braces.
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2022-12-11 15:26:42 +01:00 |
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Brian Taylor
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5726c9ff0b
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Tidy up debug tracing code.
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2022-12-11 15:26:16 +01:00 |
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Brian Taylor
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aa2f3b7bbb
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Fix memory leaks.
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2022-12-11 15:25:52 +01:00 |
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Brian Taylor
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4294f49968
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Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
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2022-12-11 15:25:24 +01:00 |
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Brian Taylor
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cefa6b380c
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When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary.
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2022-12-11 15:25:00 +01:00 |
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Brian Taylor
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029df5a3d6
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Check that the bparse gen_tab optimization loop finishes when no more improvements occur.
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2022-12-11 15:24:35 +01:00 |
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Brian Taylor
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aff20b9db1
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Remove asserts, replace fixed size lexer_buf.
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2022-12-11 15:21:09 +01:00 |
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Brian Taylor
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d54c1fc091
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Add pindly tristate example. Cleanup error handling.
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2022-12-11 15:20:27 +01:00 |
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Brian Taylor
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0627af435a
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Remove most asserts.
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2022-12-11 15:20:03 +01:00 |
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Brian Taylor
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b142be7fde
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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2022-12-11 15:19:39 +01:00 |
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Brian Taylor
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4e76586b6b
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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2022-12-11 15:19:17 +01:00 |
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Brian Taylor
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13c01abf0d
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Fix a typo, add more comments.
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2022-12-11 15:18:52 +01:00 |
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Brian Taylor
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68f0d49f58
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Add support for TRISTATE: in PINDLY.
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2022-12-11 15:18:32 +01:00 |
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Brian Taylor
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363179ce2f
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Fix potential memory leak, clean out debug code.
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2022-12-11 15:18:12 +01:00 |
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Brian Taylor
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499bef097e
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Better estimates of rise/fall delays in PINDLYs with outputs separated by CASE.
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2022-12-11 15:17:51 +01:00 |
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Brian Taylor
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a01edf2f36
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Fix visualc compiler warnings.
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2022-12-11 15:17:33 +01:00 |
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Brian Taylor
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22a3af8a1e
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Improve delay estimates for pindly output buffers.
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2022-12-11 15:17:17 +01:00 |
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Brian Taylor
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64c2c1ee05
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Initial handling of PINDLY. Output buffers without rise/fall delay estimates.
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2022-12-11 15:16:57 +01:00 |
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Brian Taylor
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62aab3885d
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Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards.
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2022-12-11 15:16:37 +01:00 |
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Brian Taylor
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7c699a599f
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Fix potential memory leak.
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2022-12-11 15:16:20 +01:00 |
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Brian Taylor
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a54aa4d1f7
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Initial logicexp parser and gate generator.
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2022-12-11 15:16:02 +01:00 |