e5bf2db785
Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
2022-11-26 09:40:35 -08:00
3f1e860a3e
Merge branch 'pre-master' into bt_dev
2022-11-25 06:48:43 -08:00
9fbf2acceb
Move digital examples to new locations
2022-11-24 16:47:59 +01:00
f7c038466b
The 8th parameter on a voltage or current source now is 'number of pulses'.
...
Previous usage had been PHASE, introduced by XSPICE, which has
been redundant to DELAY. PHASE is again available when compatibility flag
xs has been set.
2022-11-24 14:46:54 +01:00
d763b39ec3
Add a new compatibility mode xs (for XSPICE)
2022-11-24 14:43:16 +01:00
77bd773ce4
Examples for 74*568 behavioral subckts.
2022-11-22 15:50:05 -08:00
8162418df9
Merge branch 'pre-master' into bt_dev
2022-11-22 08:35:57 -08:00
f2be3d681d
Allow resetting the limit for warning mesaages, when a new run is started.
2022-11-20 15:07:46 +01:00
8b85302da1
Replace obscure warning "singular matrix: check nodes mymode1 and mynode1" by
...
"singular matrix: check node mynode1", if both node names are equal.
2022-11-20 12:10:40 +01:00
2ec9e6a38e
Add more debug instrumentation.
2022-11-18 14:41:25 +01:00
b31b4759e6
Use tilde '~' inputs instead of creating inverters.
2022-11-18 14:41:08 +01:00
ef86fcd6bd
Remove mentioning line number 0, which has been incomprehensible.
2022-11-18 14:38:29 +01:00
8e5c76d8b3
Add error messages when controlled_exit is called:
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No exit without message.
2022-11-16 11:37:35 +01:00
bb2574a38e
Merge branch 'pre-master' into bt_dev
2022-11-15 15:04:21 -08:00
96a9726b19
Add more debug instrumentation.
2022-11-15 14:59:58 -08:00
ffe920117c
calculate log frequency sweep such that start frequency and stop frequency are always exactly included
2022-11-14 11:34:49 +01:00
c4247c4353
fix: allow hicum/l2 to compile with older c++ compilers
2022-11-14 10:25:03 +01:00
84833ccc97
Use tilde '~' inputs instead of creating inverters.
2022-11-12 22:53:49 -08:00
9d13e5dc43
Merge branch 'pre-master' into bt_dev
2022-11-12 22:24:31 -08:00
fcc3191732
rename example file
2022-11-12 14:52:22 +01:00
0ea6dd8322
Examples moved to folder /various
2022-11-12 14:49:01 +01:00
7cf6b1f12b
Examples for d_pwm and d_osc
2022-11-12 14:47:57 +01:00
743f20d04b
Add new functions for operators x**y or x^y
...
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
2022-11-12 14:35:26 +01:00
eff183f51e
Add new functions for operators x**y or x^y
...
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
2022-11-12 14:35:01 +01:00
b147aa0c3a
Add safety braces.
2022-11-11 14:13:36 +01:00
e770d96151
Tidy up debug tracing code.
2022-11-11 14:13:28 +01:00
cd72c7960b
Fix memory leaks.
2022-11-11 14:13:22 +01:00
b0e9874de8
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
2022-11-11 14:13:03 +01:00
a922f797d3
When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary.
2022-11-11 14:12:54 +01:00
574737b7b6
Check that the bparse gen_tab optimization loop finishes when no more improvements occur.
2022-11-11 14:12:47 +01:00
539176bf15
remove unused
2022-11-11 13:41:10 +01:00
d6650e66f0
To find the nearest integer, use nearbyint(). trunc() has delivered
...
only one-sided answers.
2022-11-11 13:21:21 +01:00
5adef0cf36
AlmostEqualUlps setting has been too strict: it failed in MINGW gcc.
...
3 --> 10
2022-11-11 11:50:53 +01:00
8165f35953
Add safety braces.
2022-11-09 14:41:27 -08:00
69c1f9605c
Tidy up debug tracing code.
2022-11-09 13:26:44 -08:00
0d86539638
Trim trailing spaces
2022-11-09 15:11:13 +01:00
f9039ea238
Don't allocate memory for control array at every time step
...
Use loc instead, setting it up once during INIT
2022-11-09 15:09:52 +01:00
5765f30d8d
Fix memory leaks.
2022-11-08 19:28:23 -08:00
deb880c090
Merge branch 'pre-master' into bt_dev
2022-11-08 12:23:07 -08:00
5d5b62685c
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
2022-11-08 12:09:13 -08:00
4a4dee88af
When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary.
2022-11-08 04:42:04 -08:00
5cecd039f6
Check that the bparse gen_tab optimization loop finishes when no more improvements occur.
2022-11-07 13:47:45 -08:00
94a0030fde
Add logicexp.c to fftw and shared project files
2022-11-07 17:50:21 +01:00
104afe77cb
Remove asserts, replace fixed size lexer_buf.
2022-11-07 14:47:57 +01:00
f9236131ff
Typo, 2 x1 subcircuits.
2022-11-07 14:47:46 +01:00
d05689eed8
Add pindly tristate example. Cleanup error handling.
2022-11-07 14:47:36 +01:00
f6386bda0c
Remove most asserts.
2022-11-07 14:47:29 +01:00
1200092250
Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
2022-11-07 14:47:18 +01:00
ab7634e72e
Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
2022-11-07 14:47:13 +01:00
77d56eb184
Fix a typo, add more comments.
2022-11-07 14:47:02 +01:00
Brian Taylor
Holger Vogt
Pascal Kuthe