Holger Vogt
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3a283b2630
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Update the example structure for OSDI/OpenVAF:
all compiled models into lib/ngspice
spinit updated to load the models via command 'osdi'
local calls with 'pre_osdi' commanted out.
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2023-01-25 13:12:27 +01:00 |
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Holger Vogt
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52577d2f26
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Nice looking Roessler Attractor
provided by A. Gillespie
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2023-01-24 15:14:23 +01:00 |
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Holger Vogt
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9bb230d6c9
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MOS example files updated and moved to its own directory
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2023-01-24 10:38:50 +01:00 |
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Holger Vogt
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19ae6bdce7
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Various filter examples using Laplace expression x_fer
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2023-01-14 23:10:46 +01:00 |
dwarning
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35b8b59555
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rm vacode
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2023-01-12 16:37:07 +01:00 |
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dwarning
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35b1cc59e3
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rm vacode
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2023-01-12 16:35:03 +01:00 |
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dwarning
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51d732a7ba
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white spaces and format
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2023-01-12 15:07:11 +01:00 |
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dwarning
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ab6ff4a934
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initialize vacode osdi examples
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2023-01-12 12:34:32 +01:00 |
Giles Atkinson
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803168bdf2
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Add a simple example of using string-valued parameters.
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2023-01-09 16:20:26 +01:00 |
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Holger Vogt
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111ec29e61
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Rename example file
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2023-01-09 16:14:25 +01:00 |
Brian Taylor
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2bba40f2c5
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Add serial load to 74f524 example.
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2023-01-08 09:19:40 +01:00 |
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dwarning
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b6f5e5b5a8
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special ngbehavior needed
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2023-01-02 14:48:37 +01:00 |
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Brian Taylor
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b0000c6eda
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Add example for 74f524.
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2022-12-31 15:03:43 +01:00 |
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Holger Vogt
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af902ed975
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Rename projetc to OR (OR-gate)
Add new path (absolute, so has to be modified by any user)
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2022-12-27 11:05:33 +01:00 |
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Holger Vogt
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0fb80096b0
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Rename examples for ECL OR gate
Simulate OR gate faster TSTEP 0.1n -> 0.3n
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2022-12-23 16:47:51 +01:00 |
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Holger Vogt
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cb970949f3
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Missing renaming: osdi_win --> osdi_libs
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2022-12-21 23:21:18 +01:00 |
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Holger Vogt
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a62507a402
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Remove
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2022-12-19 14:31:09 +01:00 |
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Holger Vogt
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5c3e255f9f
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Move adder_common.inc to be available for all test files.
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2022-12-19 14:30:13 +01:00 |
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Holger Vogt
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bb7034b559
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Rename test_osdi_libs to osdi_libs
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2022-12-19 10:44:59 +01:00 |
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Holger Vogt
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b1e70f05a0
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Update with Semimod download page
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2022-12-17 14:35:05 +01:00 |
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Holger Vogt
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88cbb4f0fe
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Rename test_osdi_win to test_osdi_libs
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2022-12-17 14:30:59 +01:00 |
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Holger Vogt
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745172df54
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Mextram models: plotting with thicker lines
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2022-12-17 14:13:04 +01:00 |
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Holger Vogt
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842c595fdc
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Update to the examples for osdi
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2022-12-16 21:55:22 +01:00 |
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Holger Vogt
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95b21de8a1
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Re-add optional selection of Berkeley model parameters.
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2022-12-14 13:26:02 +01:00 |
h_vogt
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831382cc7d
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Add log plots
Add sim vs. Temp.
Add y-labels
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2022-12-13 21:07:27 +01:00 |
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Holger Vogt
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1b121307c8
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Remove unused variable debarr.
Add another example.
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2022-12-04 10:41:22 +01:00 |
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Holger Vogt
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2b412cf470
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derivative inside of .func
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2022-12-04 10:41:17 +01:00 |
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Holger Vogt
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288d60b8cb
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simple example for derivative in B source
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2022-12-04 10:41:11 +01:00 |
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Holger Vogt
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91a5ceb722
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add linewidth for graphs
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2022-12-04 10:32:59 +01:00 |
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Holger Vogt
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b5d0ed4590
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tiny update, typos, font size
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2022-12-04 10:32:32 +01:00 |
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Brian Taylor
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44c69f5bf5
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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2022-11-28 22:33:00 +01:00 |
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Brian Taylor
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de2280ca73
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Examples for 74*568 behavioral subckts.
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2022-11-28 22:32:53 +01:00 |
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Holger Vogt
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9fbf2acceb
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Move digital examples to new locations
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2022-11-24 16:47:59 +01:00 |
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Holger Vogt
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fcc3191732
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rename example file
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2022-11-12 14:52:22 +01:00 |
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Holger Vogt
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0ea6dd8322
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Examples moved to folder /various
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2022-11-12 14:49:01 +01:00 |
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Holger Vogt
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7cf6b1f12b
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Examples for d_pwm and d_osc
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2022-11-12 14:47:57 +01:00 |
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Brian Taylor
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b0e9874de8
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Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
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2022-11-11 14:13:03 +01:00 |
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Brian Taylor
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f9236131ff
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Typo, 2 x1 subcircuits.
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2022-11-07 14:47:46 +01:00 |
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Brian Taylor
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d05689eed8
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Add pindly tristate example. Cleanup error handling.
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2022-11-07 14:47:36 +01:00 |
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Brian Taylor
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1200092250
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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2022-11-07 14:47:18 +01:00 |
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Brian Taylor
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ab7634e72e
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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2022-11-07 14:47:13 +01:00 |
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Holger Vogt
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dc8c7db718
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Fix a bug in simple diode, when ilimit is set, but not epsilon.
Make model more similar to LTSPICE
Add an example
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2022-09-29 16:14:25 +02:00 |
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Giles Atkinson
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c75476eaa0
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Add some automatic bridge examples, mostly using the bidirectional bridge.
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2022-09-23 13:15:07 +02:00 |
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Holger Vogt
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fb75a15e83
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example for pwlts source code model
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2022-09-09 15:26:45 +02:00 |
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Holger Vogt
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0be7461dd9
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Enable power measurement for W switch
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2022-08-29 20:30:23 +02:00 |
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Holger Vogt
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c70a438ae0
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Replace end-of-line comment delimiter $ by ;
So to make it independent from compatibility switch selection.
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2022-08-29 14:19:47 +02:00 |
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Holger Vogt
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6b786099cb
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examples for .probe alli or .probe i(xx)
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2022-08-29 14:11:20 +02:00 |
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Holger Vogt
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ef3adfc050
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set colors for grids and data
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2022-08-28 17:52:55 +02:00 |
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Brian Taylor
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0e0daa7d9a
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Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test.
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2022-08-06 10:42:56 +02:00 |
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Holger Vogt
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03bd381e83
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aswitch needs two input nodes because gd has been selected for input.
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2022-08-05 17:30:51 +02:00 |