Rename examples for ECL OR gate

Simulate OR gate faster TSTEP 0.1n -> 0.3n
This commit is contained in:
Holger Vogt 2022-12-23 16:47:51 +01:00
parent dacbf453ab
commit 0fb80096b0
4 changed files with 82 additions and 1 deletions

View File

@ -16,10 +16,12 @@ R3 GND Net-_Q3-Pad2_ 575
Ra2 A2 VEE 510
V3 In2 GND dc -1.75 pulse(-1.75 -0.9 0 1n 1n 2.5u 5u)
Rt1 DT GND 1G
.tran 0.1n 100u
.tran 0.3n 100u
.control
pre_osdi osdi_libs/HICUML0-2.osdi
run
rusage
set xbrushwidth=2
plot a1 a2+2 in1+4 in2+6
.endc
.end

View File

@ -0,0 +1,75 @@
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View File

@ -819,6 +819,10 @@
(uuid fffeed8b-d6ec-4440-8197-319371f73fce)
)
(text "ECL OR - NOR gate" (at 245.364 87.884 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 323369ca-7b3f-476e-866f-1c1d7820c037)
)
(text ".tran 0.1n 100u\n.control\npre_osdi test_osdi_win/HICUML0-2.osdi\nrun\nplot a1 a2+2 in1+4 in2+6\n.endc"
(at 242.824 120.142 0)
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