fd3827af40
Fix ordering of parameter definition and use.
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Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
2025-05-24 11:00:18 +02:00
35968d1da6
Add additional examples of Verilog co-simulation and share the Verilog
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source and large parts of the example circuits between Verilator and
Icarus Verilog. Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
2024-11-02 22:30:32 +01:00
c18447f9f5
Add the support files for co-simulation with Verilog code
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compiled by Verilator. Also add script files to Visual Studio builds
that are already installed by the Makefile builds.
2023-11-27 20:55:59 +00:00
Giles Atkinson