ngspice

Commit Graph

Author	SHA1	Message	Date
Giles Atkinson	fd3827af40	Fix ordering of parameter definition and use. Icarus Verilog no longer accepts use-before-definition. Also slightly expand the README for Icarus Verilog examples.	2025-05-24 11:00:18 +02:00
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2024-11-02 22:30:32 +01:00

Author

SHA1

Message

Date

Giles Atkinson

fd3827af40

Fix ordering of parameter definition and use.

Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.

2025-05-24 11:00:18 +02:00

Giles Atkinson

35968d1da6

Add additional examples of Verilog co-simulation and share the Verilog

source and large parts of the example circuits between Verilator and
Icarus Verilog.  Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.

2024-11-02 22:30:32 +01:00

2 Commits