Brian Taylor
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b79eca646b
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Prevent crashes in udevices.c when malformed U* instances are present. This would happen with incorrectly written U* gates, ff, latches which do not conform to the PSpice specs. Instead, ERROR messages are output which, hopefully, will help a user to debug their subckt.
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2023-07-31 14:26:01 +02:00 |
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Brian Taylor
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6b85bcb805
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Allocate compound gate connectors where needed.
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2023-05-27 10:41:04 +02:00 |
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Brian Taylor
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de34a90bb4
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Create correct translations of degenerate compound gates with $d_hi/$d_lo inputs.
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2023-05-27 10:40:51 +02:00 |
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Brian Taylor
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14a403e193
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Use ~ on the input of a tristate buffer for INV3, and avoid creating an extra inverter. For ff/latch use ~ on set/reset and jkff clock inputs to avoid creating extra inverters.
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2023-05-27 10:38:40 +02:00 |
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Brian Taylor
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40a540a2ff
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Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays.
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2023-03-22 14:26:18 +01:00 |
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Brian Taylor
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164db58404
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The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE.
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2023-03-22 14:25:51 +01:00 |
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Brian Taylor
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a6b2773c90
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For a ugate timing model, when tphlXX/tplhXX is not found, set the fall/rise delay to zero (1.0e-12).
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2023-03-18 14:36:35 +01:00 |
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Brian Taylor
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0e5a5a62ac
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74F550 and 74F551 have only fall delays on the inverters. Use the fall delay for both rise and fall.
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2023-03-18 14:36:23 +01:00 |
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Brian Taylor
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3a76a1ef52
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Prepare for inertial_delay model parameter.
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2023-03-18 14:36:17 +01:00 |
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Brian Taylor
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4b30113f60
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Check current_subckt is set when printing TRANS_OUT.
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2023-03-18 14:36:00 +01:00 |
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Brian Taylor
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56d0c72924
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Add port directions when logicexp or pindly are present.
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2023-02-01 17:39:37 +01:00 |
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Brian Taylor
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9c9301eca8
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Remove delay ifdefs.
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2023-02-01 17:38:28 +01:00 |
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Brian Taylor
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f674b64264
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Remove dead code from previous commit.
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2023-02-01 17:37:36 +01:00 |
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Brian Taylor
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f570b04d6c
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For unspecified gate delays (logic and tristate gates), which PSpice would consider as zero, set the rise and fall delays to 1.e-12s (the minimum for Xspice). For dff, jkff, dlatch, and srlatch use the Xspice default 1.0ns for rise and fall delays. If the ngspice variable (ps_port_directions & 2) is true, write the translated subckt to stdout, with TRANS_OUT prefix, for debugging purposes. The user could edit and replace the translated subckt if desired.
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2023-02-01 17:36:36 +01:00 |
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Brian Taylor
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dcfe4e7134
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ERROR messages should be printed to stderr.
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2023-01-15 13:37:42 +01:00 |
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Brian Taylor
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a76f8d5149
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Fix some comments.
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2023-01-09 16:33:25 +01:00 |
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Brian Taylor
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6117836d01
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Ensure that amatch output is not binary data.
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2023-01-09 16:30:22 +01:00 |
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Brian Taylor
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90ec717f3b
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Add variable ps_udevice_exit. If set non-zero, ngspice will exit if there is an error processing f_logicexp or f_pindly.
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2023-01-09 16:29:24 +01:00 |
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Brian Taylor
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5e6452099e
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Return errors from f_logicexp and f_pindly without calling exit.
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2023-01-09 16:29:08 +01:00 |
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Brian Taylor
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0805856fb7
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Distinguish between set/reset delays when possible.
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2022-12-19 12:43:00 +01:00 |
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Brian Taylor
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253df17949
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Make it optional to use zl/zh/lz/hz delays for utgate.
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2022-12-19 12:42:36 +01:00 |
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Brian Taylor
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4c457a3cd4
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Avoid unnecessary calculations for utgate.
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2022-12-19 12:42:06 +01:00 |
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Brian Taylor
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a4b609fb6a
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For utgate timing models, if hl/lh are not present use zl/zh/lz/hz to give a more accurate tristate delay.
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2022-12-19 12:41:18 +01:00 |
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Brian Taylor
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021982799e
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More conservative delay estimates for timing model type ugff.
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2022-12-19 12:40:50 +01:00 |
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Brian Taylor
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11f6eace68
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For dff/jkff, obtain more conservative estimates for clk_delay, set_delay and reset_delay.
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2022-12-19 12:40:06 +01:00 |
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Brian Taylor
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47260e2eb8
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Rewrite extract_model_param.
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2022-12-11 15:38:08 +01:00 |
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Brian Taylor
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0924fbb7eb
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Modify the delay calculation for non-conforming timing model in .subckt CD4572UB.
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2022-12-11 15:37:34 +01:00 |
Giles Atkinson
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73e8fed0fc
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Fix warnings from gcc 10.2.1.
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2022-12-11 15:35:14 +01:00 |
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Brian Taylor
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7ff8f3773f
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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2022-12-11 15:34:33 +01:00 |
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Brian Taylor
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b142be7fde
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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2022-12-11 15:19:39 +01:00 |
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Brian Taylor
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4e76586b6b
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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2022-12-11 15:19:17 +01:00 |
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Brian Taylor
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62aab3885d
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Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards.
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2022-12-11 15:16:37 +01:00 |
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Brian Taylor
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a54aa4d1f7
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Initial logicexp parser and gate generator.
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2022-12-11 15:16:02 +01:00 |
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Brian Taylor
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4a904cdf18
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Add drive 0/1 for $d_lo/$d_hi.
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2022-12-11 15:15:44 +01:00 |
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Brian Taylor
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150839dd1a
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Remove VisualC compile warnings.
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2022-10-09 10:21:51 +02:00 |
Holger Vogt
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2547115eeb
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Prevent Visual Studio compiler warnings
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2022-10-09 10:21:06 +02:00 |
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Brian Taylor
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bd00738a49
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Fix memory leaks in ff/latch code.
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2022-10-08 16:50:03 +02:00 |
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Brian Taylor
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e2652d813d
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If ps_udevice_msgs >= 2, print complete line of unsupported PSpice instance. For debugging purposes.
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2022-10-08 16:49:38 +02:00 |
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Brian Taylor
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e703bd9142
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Add comment about ps_udevice_msgs variable. Set to 1 will print PSpice instance names and types which are not supported and are found when processing a subckt.
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2022-10-07 13:48:37 +02:00 |
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Brian Taylor
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e9855be595
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If variable ps_port_directions >= 2, also show the translated Xspice statements.
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2022-10-07 13:48:05 +02:00 |
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Brian Taylor
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3ca91aa1ac
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Make a trivial change to support (n)and3a, (n)or3a, (n)xor3a types. These are not used in any of the Micro Cap libraries. Completes support for Pspice tristate gate types.
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2022-10-07 13:15:45 +02:00 |
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Brian Taylor
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abd4af1ae6
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Ignore IO models in a subckt. Setting variable ps_port_directions to a non-zero int prints the directions (IN, OUT, INOUT) of subckt ports.
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2022-10-07 13:14:58 +02:00 |
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Brian Taylor
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2d9f86c742
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Check for name collisions between nodes generated during translation from Pspice to Xspice and instance pin or subckt port names. These are reported as ERRRORs.
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2022-10-07 13:14:35 +02:00 |
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Brian Taylor
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b6db33f472
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There needs to be 2 variants of d0_gff. One for d_dlatch, the other for d_srlatch.
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2022-10-07 12:56:37 +02:00 |
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Brian Taylor
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a8f103eebc
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Clean out dead code in model processing.
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2022-10-07 12:56:14 +02:00 |
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Brian Taylor
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1a00a30f18
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Add support for srff.
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2022-10-07 12:55:59 +02:00 |
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Brian Taylor
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7f38ce4ebb
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Remove debug code.
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2022-10-07 12:55:42 +02:00 |
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Brian Taylor
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648218d5a8
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Remove invalid check.
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2022-10-07 12:55:25 +02:00 |
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Brian Taylor
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6a067378cb
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Add optional debug code to check for name collisions. Connector nodes between gates now have a con_ prefix.
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2022-10-07 12:55:06 +02:00 |
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Brian Taylor
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5b3862ebc7
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Prevent multiple d_zero_inv99 models per subckt.
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2022-10-07 12:54:54 +02:00 |