c46866d688
Fix some typos.
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Thanks to Brian for checking.
2023-12-18 20:13:06 +01:00
c69018fe82
Enable measurements with ?-sweep (v, i, temp, or res).
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Improve error messages.
Prevent crash is compüdata is not available.
Add to examples for measure failures.
2023-12-09 15:43:15 +01:00
1adee64224
Add scripts for running the paranoia tests in parallel on Linux with valgrind.
2023-12-04 15:12:15 +01:00
c18447f9f5
Add the support files for co-simulation with Verilog code
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compiled by Verilator. Also add script files to Visual Studio builds
that are already installed by the Makefile builds.
2023-11-27 20:55:59 +00:00
f6f7319792
Add null-pointer checks to some code that crashed when trying
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to .print results from a non-existent analysis. Also remove the
troublesome .plot and .print lines from two examples.
2023-11-09 12:07:31 +00:00
826cddb483
add examples for OSDI noise
2023-11-04 19:36:30 +01:00
f66e0bf2ac
implement osdi noise support
2023-11-04 19:36:30 +01:00
864ef7925c
Add notes on the structure and organization of an external d_process program.
2023-10-28 19:43:50 +02:00
5c6b9f03b5
Fix the zero count.
2023-10-28 19:43:41 +02:00
1f5f7ae439
Update d_process examples.
2023-10-28 19:43:36 +02:00
09f070f582
Error handling improvements in cfunc.mod. Ensure that d_process.h wiil always respond to version and interface checks sent from sendheader. This is needed so that the pipe reads in sendheader do not cause Windows to hang when the interface version and in/out counts do not match. This hang was the cause of errors not being reported and the Windows gui hanging. Startup and header checks are now detected in cm_d_process, and the simulator will run but with runtime errors since a d_process model cannot be completely instantiated after initial errors. It would be good to find a means of gracefully halting the simulation run.
2023-10-28 11:00:33 +02:00
4530cde8e2
Use Xspice cm_message_send to report errors rathen than printing to stderr and calling exit. When a d_process model has errors found in start(), sendheader(), and dprocess_exchangedata() these are reported, but if the model is run a SIGINT is raised. There must be a better way of stopping the simulator.
2023-10-28 11:00:18 +02:00
182764a894
Add examples/xspice/d_process.
2023-10-28 11:00:12 +02:00
046be0cdc8
Use the PSP103 model pspnqs103va (including nqs option)
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as this is the standard in the IHP Open PDK.
2023-10-27 23:25:42 +02:00
4b226bf11c
add output for all noise sources
2023-10-11 09:52:44 +02:00
77c4cb5452
new bipolar noise example
2023-10-11 09:52:10 +02:00
f2247a3c6f
Use sparse, as KLU will fail.
2023-09-10 13:43:09 +02:00
716bb0a6bc
Add plot for inverter gain
2023-08-30 14:23:25 +02:00
161ace44da
Restore the original model parameters.
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Add information on its source.
2023-08-28 12:11:20 +02:00
b08eb2266a
Added initial KLU support for node collapsing
2023-08-16 11:14:24 +02:00
bb90374402
Added missing ISCAS85 libraries
2023-08-16 11:14:18 +02:00
ba4e530ec0
KLU Integration from scratch #1 , examples/klu/Circuits
2023-08-16 11:14:09 +02:00
f60766a1fa
Transformer examples, (three different methods)
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Single primary and secondary windings
More to come (multiple ports, core saturation)
2023-08-11 11:38:52 +02:00
4f22726c87
better low Ic range covering
2023-08-11 11:38:09 +02:00
5704790cc2
no need for extra run
2023-08-11 11:37:37 +02:00
8bd3c87be1
better visibility
2023-07-31 14:30:37 +02:00
5fe236290f
Add example of reading S-parameters from a Touchstone file.
2023-07-31 14:30:02 +02:00
f632da5f7f
Add a comment to say that LT/PSPICE compatability is needed.
2023-07-31 14:29:50 +02:00
68f1015075
Example for 7490a Pspice subckt. This exercises jkff, logicexp, and pindly conversions to XSPICE.
2023-07-31 14:27:59 +02:00
576f218945
Fix the NAND and NOR variants of XSPICE code model multi_input_pwl
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and add an example of its use with the E-source NAND variant.
2023-07-31 14:25:40 +02:00
51b361bbf0
When Cider models are present, a normal batch mode sp_shutdown (for example, ngspice -b cmosinv.cir) will call com_quit(NULL). This cleans up so that valgrind will find no leaks in Cider devices after sp_shutdown. To disable this feature, set the environment variable CIDER_COM_QUIT="OFF". Even though it really does not matter that Cider memory is cleared just before exit, it makes it cleaner for valgrind checks.
2023-07-15 11:32:37 +02:00
5114d6c2f4
Add an option to the iplot command: -d sets the number of simulation
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steps before the window is shown. The value can be chosen to
limit rapid resizing when starting and that is used in the PLL examples.
2023-07-15 11:29:32 +02:00
d31568bd83
Add parsing and translation of the FREQ form of E-source devices,
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integrated with the existing parsing of AND/NAND/OR/NOR forms (inpcom.c).
For the implementation, add a new analog XSPICE code model, xfer.
Add an example to examples/sp.
2023-07-15 11:15:08 +02:00
585f13bd4a
Better visibility of the results
2023-07-15 11:11:48 +02:00
c7bb12d9d0
More info
2023-05-27 10:49:32 +02:00
5c8af9770b
Add rusage to measure simulation time.
2023-05-27 10:48:07 +02:00
2685df1b05
Add vto model parameter (the default has changed!), add .ic
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to ease op and immediately start oscillation.
2023-05-27 10:47:43 +02:00
a48cc44c7f
Example input file for 'iplot -w' option
2023-05-27 10:46:55 +02:00
a48b36ffc5
more realistic self-heating example
2023-05-27 10:39:55 +02:00
14a403e193
Use ~ on the input of a tristate buffer for INV3, and avoid creating an extra inverter. For ff/latch use ~ on set/reset and jkff clock inputs to avoid creating extra inverters.
2023-05-27 10:38:40 +02:00
33e17fa969
noise simulation examples
2023-04-02 22:56:49 +02:00
7f4eb1c7d8
Add examples of controlling auto-bridge behaviour
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with the "vcc" and "family" parameters.
2023-04-01 13:56:23 +02:00
6213145c94
.control section: atanh examples
2023-03-18 22:32:34 +01:00
c2fb32f98a
really run a dc simulation
2023-03-18 14:30:23 +01:00
d36c4b8772
Remove bulk simulation netlist from files
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needing a .control section.
2023-01-28 17:02:13 +01:00
8c98b70e45
Add input file dedicated to batch mode,
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to be run with
ngspice -b -r inv.out bsimbulk_inverter_bach.sp
2023-01-28 17:01:53 +01:00
512bcf6095
Remove unused folder
2023-01-28 17:01:37 +01:00
dbdbcf95c2
BSIMBULK example with locally adding osdi models
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by using the 'pre_osdi' command in a .control section
2023-01-28 17:01:22 +01:00
b9eef23eed
Update the example structure for OSDI/OpenVAF:
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all compiled models into lib/ngspice
spinit updated to load the models via command 'osdi'
local calls with 'pre_osdi' commanted out.
2023-01-27 16:08:17 +01:00
5bd45eeb87
The Roessler Attractor examples has been provided by
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Giles Atkinson, of course
2023-01-24 16:29:50 +01:00
16c7c407d4
Nice looking Roessler Attractor
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provided by A. Gillespie
2023-01-24 15:17:45 +01:00
cb5f9e9bdc
MOS example files updated and moved to its own directory
2023-01-24 15:17:31 +01:00
af9f25e985
Various filter examples using Laplace expression x_fer
2023-01-20 15:07:37 +01:00
bf580abf69
Add a simple example of using string-valued parameters.
2023-01-09 16:33:53 +01:00
01c211339c
Rename example file
2023-01-09 16:33:38 +01:00
4936fa2b1d
Add serial load to 74f524 example.
2023-01-09 16:33:10 +01:00
0cae4f0b6c
special ngbehavior needed
2023-01-09 16:31:01 +01:00
c7fd3bcaee
Add example for 74f524.
2023-01-09 16:30:42 +01:00
4bcd4daf55
Rename projetc to OR (OR-gate)
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Add new path (absolute, so has to be modified by any user)
2022-12-27 14:22:07 +01:00
b639ebae44
Rename examples for ECL OR gate
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Simulate OR gate faster TSTEP 0.1n -> 0.3n
2022-12-27 14:21:24 +01:00
3e27e640b5
Missing renaming: osdi_win --> osdi_libs
2022-12-27 14:19:58 +01:00
4f73f18f6d
Remove
2022-12-27 14:19:18 +01:00
69660ad387
Move adder_common.inc to be available for all test files.
2022-12-27 14:18:54 +01:00
bb9469a03a
Rename test_osdi_libs to osdi_libs
2022-12-27 14:14:01 +01:00
96608abbe2
Update with Semimod download page
2022-12-27 14:13:27 +01:00
157200aa86
Rename test_osdi_win to test_osdi_libs
2022-12-27 14:13:02 +01:00
a211a90e5a
Mextram models: plotting with thicker lines
2022-12-27 14:12:41 +01:00
ac73e6f7b7
Update to the examples for osdi
2022-12-27 14:12:10 +01:00
d7bdfe1a20
Re-add optional selection of Berkeley model parameters.
2022-12-19 12:43:55 +01:00
5ec6543dbb
Add log plots
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Add sim vs. Temp.
Add y-labels
2022-12-19 12:43:27 +01:00
e28d3feee0
Remove unused variable debarr.
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Add another example.
2022-12-11 15:39:10 +01:00
45574cecb2
derivative inside of .func
2022-12-11 15:38:49 +01:00
89a48e7d73
simple example for derivative in B source
2022-12-11 15:38:37 +01:00
082ae1603e
add linewidth for graphs
2022-12-11 15:36:57 +01:00
058e7a34f8
tiny update, typos, font size
2022-12-11 15:36:42 +01:00
7ff8f3773f
Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
2022-12-11 15:34:33 +01:00
cd883d23d6
Examples for 74*568 behavioral subckts.
2022-12-11 15:33:53 +01:00
5324319edb
Move digital examples to new locations
2022-12-11 15:33:08 +01:00
925dc55a73
rename example file
2022-12-11 15:28:23 +01:00
ca1974ff37
Examples moved to folder /various
2022-12-11 15:28:01 +01:00
751019b447
Examples for d_pwm and d_osc
2022-12-11 15:27:42 +01:00
4294f49968
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
2022-12-11 15:25:24 +01:00
d425beb557
Typo, 2 x1 subcircuits.
2022-12-11 15:20:49 +01:00
d54c1fc091
Add pindly tristate example. Cleanup error handling.
2022-12-11 15:20:27 +01:00
b142be7fde
Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
2022-12-11 15:19:39 +01:00
4e76586b6b
Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
2022-12-11 15:19:17 +01:00
43de22ec24
Update to the examples: enable plotting with option digitop
2022-10-24 17:05:34 +02:00
0aff89dc28
Example for URC distributed RC transmission line
2022-10-22 16:00:15 +02:00
ec6a902fb9
Fix a bug in simple diode, when ilimit is set, but not epsilon.
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Make model more similar to LTSPICE
Add an example
2022-10-08 16:50:38 +02:00
b212a49982
Add some automatic bridge examples, mostly using the bidirectional bridge.
2022-10-08 16:48:36 +02:00
cb42895dad
example for pwlts source code model
2022-10-07 13:39:33 +02:00
d39c60542d
Enable power measurement for W switch
2022-10-07 13:18:51 +02:00
fe8eb26aaf
Replace end-of-line comment delimiter $ by ;
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So to make it independent from compatibility switch selection.
2022-10-07 13:18:29 +02:00
f1eb8d3955
examples for .probe alli or .probe i(xx)
2022-10-07 13:17:55 +02:00
3dbfc934bb
set colors for grids and data
2022-10-07 13:17:06 +02:00
4706c3dea5
Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test.
2022-10-07 13:15:23 +02:00
e9b5a9a957
aswitch needs two input nodes because gd has been selected for input.
2022-10-07 13:13:38 +02:00
c8ed9590b7
Handle the case when control voltages on and off are equal.
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Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
2022-10-07 13:12:56 +02:00
5b0b328186
If a node name to be plotted ends by ':power', its type is set to POWER.
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Thus 'settype power nodename(s)' in the examples is no longer necessary.
2022-10-07 13:12:04 +02:00
2deefe1fbc
New tables for MOS devices
2022-10-07 13:11:18 +02:00
Holger Vogt
Brian Taylor
Giles Atkinson
Pascal Kuthe
Francesco Lannutti
Francesco Lannutti
dwarning
h_vogt