"Initial transient solution assumes voltage source=0 even if it is not."
Cause was another error in ad5bb9eb8d, fix for Bug #607, which uncovered
an earlier latent bug.
It does add missing { and } when event-driven instances are not present.
Without this change CKTop will always be called again directly in NOISEan even
if CKTop was previously called by EVTop. This matches the intended
behavior before #ifdef KLU was added.
is defined in the .model statement. This may help achieving
convergence if subcircut models of opamps etc use simple diodes
as voltage limiters. Example call:
.options diode_cj0=20p diode_rser=20m
("Set lower case for variables or vectors in command 'echo'.
Tokens starting with '$' will get lower-casing.", 2024-09-07)
Don't use s as name for temporary string, as s has been set
already and is used later.
using an extra line 'Command: ...').
The old sequence (adding commands manually to raw file) is
still available.
The 'Command: anycommand' will not be executed if loading
an ngspice-generated raw file. Raw files from other simulators may
generate a warning that the command is not available.
of the d_cosim codemodel, using libvvp, the simulation runtime of
Icarus Verilog. This complements the existing method using Verilator.
The new source code is built into two binary shared libraries,
ivlng.so (or .DLL) and ivlng.vpi that are loaded during simulation.
in Verilog source code. Also add two parameters to d_cosim:
sim_args is used to pass string arguments to a Verilator simulation;
and lib_args is for future use. In vlnggen, also check for two causes
of failure: a verilator error may lead to creation of interfering header
files; and misleading instances of verilated_shim.cpp can cause an obscure
failure (reported by Diarmuid Collins).
Use a generic name for the generated DLL in MSVC.CMD.
Holger Vogt
Árpád Bűrmen
Giles Atkinson
Brian Taylor
Alessio Cacciatori
Francesco Lannutti
dwarning
Vogt