6eeb48bb5a
Remove obsolete READMEs from distribution, add new and interesting ones
2023-03-27 15:52:19 +02:00
6060a2fb93
typos
2023-03-27 10:03:10 +02:00
95c4c0f587
Add inertial.h to the distributable headers
2023-03-25 15:36:15 +01:00
c4c77211e9
Prepare ngspice-40
2023-03-25 13:08:51 +01:00
806489860f
Prepare for ngspice-40
2023-03-24 23:47:10 +01:00
311ddeac0d
Prepare for ngspice-40
2023-03-24 22:27:12 +01:00
062785319a
When '.probe alli' is set, disable auto bridging and set a flag
2023-03-24 22:10:18 +01:00
ce38a768b5
typo
2023-03-24 22:10:12 +01:00
c30af55491
Add operating point information to SOA check,
...
using vbefwd, vbcfwd, and vsubfwd
Operating point heck is enabled by .options warn=2
2023-03-24 22:10:07 +01:00
443567dbaf
Add SOA-check for collector-substrate diode (model parameter bvsub)
2023-03-24 22:09:55 +01:00
ff77c583d7
Add model parameter selft, to switch on self-heating, default: off (selft=0)
2023-03-24 22:09:42 +01:00
5197200fb3
Fix crash reported by Brian Taylor. If "source" is used after
...
analysis, the circuit is both deleted and destroyed. Beware of
double frees.
2023-03-22 14:30:18 +01:00
98333ee89a
Fix a memory leak reported by Brian Taylor that was introduced
...
by commit 4d8e17487b
2023-03-22 14:30:11 +01:00
82de3db8ad
VBIC: Add bvbe, bvbc, and bvce as redundant SOA parameters
2023-03-22 14:30:01 +01:00
f121c433a7
Check for buggy diode instance line, avoid crash
2023-03-22 14:29:48 +01:00
2ce18ab184
Add VDMOS default junction cap IRF540 IRF9540
2023-03-22 14:29:37 +01:00
2a647f8462
Set default VDMOS model parameters to resemble IRF540, 9540
2023-03-22 14:29:22 +01:00
e25f8bd522
Add inertial delay to missed d_xnor and tidy blank lines in d_xor.
2023-03-22 14:29:03 +01:00
cecce5163e
Inertial delay for remaining simple gates and buffers:
...
nand or xor open_c open_e, but not tristate.
2023-03-22 14:28:51 +01:00
db38d4ad54
Correct timing of transitions to UNKNOWN.
2023-03-22 14:28:37 +01:00
240a2b9406
Add missed file inertial.h.
2023-03-22 14:28:23 +01:00
4623a04615
Interim version of inertial delay for tristate buffer.
...
This does not handle three-way or mixed transitions.
2023-03-22 14:28:15 +01:00
e3b4df6a51
First group of digital code models with improved implementation
...
of inertial delay: buffer, inverter, and, nor. Also adds
utility function cm_is_inertial(().
2023-03-22 14:27:54 +01:00
2643e3b17f
New code-model library functions cm_schedule_output() and cm_getvar().
...
To be used in the inertial delay code for digital code models.
2023-03-22 14:27:35 +01:00
c1659a64c3
Change output event setup in evtload.c so that, when making an event call
...
to a code model, there is no longer a reference to the value of the event
at the head of the free list. That allows all such free lists (with the
same data type) to be combined, probably improving performance.
This is in preparation for full implementation of inertial delay for
digital nodes.
2023-03-22 14:27:19 +01:00
2d0561f386
Allow string-valued parameters to XSPICE device models with no default.
...
The code model then sees the value NULL. Needed for the "family"
parameter on logic models, used by automatic bridge insertion.
2023-03-22 14:27:06 +01:00
8c69ada5b5
The logicexp example in the PSpice ref. manual has a name with a '+' character (LCN+4). Update lexer_scan.
2023-03-22 14:26:43 +01:00
40a540a2ff
Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays.
2023-03-22 14:26:18 +01:00
164db58404
The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE.
2023-03-22 14:25:51 +01:00
86951501a7
Add eprvcd to the commands which set node names to lower case,
...
but not the file names after >
Does not work for manually entered eprvcd commands, where the user
has to provide lower case node names.
2023-03-19 15:24:27 +01:00
6213145c94
.control section: atanh examples
2023-03-18 22:32:34 +01:00
3632a6b4ae
We need to translate from degree to rad
2023-03-18 22:32:25 +01:00
2a6052517b
Fix prvious commit: allow access to all vector elements of cc
2023-03-18 22:32:19 +01:00
68156fa62c
Complex number handling other than MSVC
2023-03-18 22:32:07 +01:00
71571a1432
Add function atanh to .control section
2023-03-18 22:31:48 +01:00
3996d27b29
Make code a little more efficient
2023-03-18 22:31:33 +01:00
7af6c4a661
Re-enable single line parameter lists, separated by commas
2023-03-18 22:31:27 +01:00
f34ff7e63c
Revert "implement typedpnjlim as optional limiter for verilog-a models"
...
This reverts commit f73d3b20a0
2023-03-18 22:31:04 +01:00
63d86f5af8
Prevent a crash in strchr
...
Reported by KiCad Sentry
2023-03-18 14:37:59 +01:00
e4202ea181
The tc for R, L, C may include an expression
...
like tc={expression} or tc={expression}, 1.3u or
tc={expression}, {expression2}
2023-03-18 14:37:53 +01:00
d8505f0069
Make error message more verbose by a hint to the line (fragment).
2023-03-18 14:37:47 +01:00
c12296182c
The code in src/frontend/subckt.c has a fixed-size structure called table at the top with a size set to N_GLOBAL_NODES = 1005. If the number of items passed in formal and actual exceeds 1005, then ngspice exits immediately with an error.
...
This patch lets table be reallocated on the fly as needed to accommodate the number of subcircuit arguments, instead of being a fixed value.
2023-03-18 14:37:40 +01:00
e4601c16ee
Not a warning but an error, stopping the simulation
2023-03-18 14:37:33 +01:00
f32f3ac8cd
Improve previous commit: A bad .model line leads to a breakup
...
of the simulation.
2023-03-18 14:37:26 +01:00
c61acefef7
Prevent crash when a bad .model line is given, like
...
.model
.model xxx
2023-03-18 14:37:19 +01:00
247562c096
Update copyright notice
2023-03-18 14:37:08 +01:00
bcec3cb5e3
Updating links to ngspice web pages
2023-03-18 14:37:02 +01:00
4cc63494db
Improve error message
...
Typo
2023-03-18 14:36:55 +01:00
4111aaf110
When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer.
2023-03-18 14:36:45 +01:00
a6b2773c90
For a ugate timing model, when tphlXX/tplhXX is not found, set the fall/rise delay to zero (1.0e-12).
2023-03-18 14:36:35 +01:00
Holger Vogt
Giles Atkinson
Brian Taylor
dwarning
R. Timothy Edwards