luke
/
ngspice
mirror of https://git.code.sf.net/p/ngspice/ngspice
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
6,365 Commits 170 Branches 63 Tags 52 MiB
Commit Graph

6365 Commits

Author SHA1 Message Date
rlar 5de9a90394 minor, readability, missing newline 2019-02-17 07:42:38 +01:00
dwarning b18e214994 add spice gmin parameter to drain and source junction current 2019-02-17 07:42:38 +01:00
dwarning 00c32de1dc remove obsolete sti and wpe model parameter 2019-02-17 07:42:38 +01:00
rlar 4f53f51ad9 ngspiceMODULEdefs.h.xml, disable EXIT_IF_ISNAN() 
don't exit() on NaN
a NaN is not necessairily a desaster,
  might be merely a sign for non-convergence,
  which still might be overcome in another try.
The bsim6 testbench case inverter_transient.sp was
  unnecessairily aborted do to NaN's
 2019-02-17 07:42:38 +01:00
rlar f6257eba84 Benchmark_test, modify for ngspice 2019-02-17 07:42:37 +01:00
rlar fa4e123b53 add Benchmark_test for BSIM6 from Berkeley 2019-02-17 07:42:37 +01:00
rlar 7534ac394c work around, 'define __TERMAL_NODE__ in bsim6.va, first successfull plot 
to work around dangling "temper" node in bsim6
fixme, adms populates the termal node slot in the matrix even though
  __TERMAL_NODE__ was not defined, leading to a singular matrix.

fixme, adms
  $port_connected
is not supported, thus just claim it to be connected.

inp2m.c, upgrade to allow bsim6 with 5 nodes
 2019-02-17 07:42:37 +01:00
rlar ea4f5e165c temporary, make the failing nodes identifyable 2019-02-17 07:41:24 +01:00
rlar 50b883dbc7 very first testcase, of course it fails 2019-02-17 07:41:23 +01:00
rlar 45575b2b1b inptyplk.c, INPtypelook(), ignore case when comparing modelname 
"bsim6" is in lower case in bsim6init.c
 2019-02-17 07:41:23 +01:00
rlar 530d69f775 ngspiceMODULEdefs.h.xml, add min max for the sake of XXXguesstopology.c 2019-02-17 07:41:23 +01:00
Guilherme Brondani Torri 865bf55961 fix callfunction 
* handle $strobe
* handle $finish
* others throw error
 2019-02-17 07:41:23 +01:00
rlar 68b8614a35 bsim6.va, macro for lln, to avoid derivatives of this function 2019-02-17 07:41:22 +01:00
rlar 4f46cd20ee bsim6.va, macro for lexp to avoid derivatives 
fixme, adsmXml can't do
  a ? b : c ? d : e
needs parentheses
  a ? b : (c ? d : e)
bug in parser
 2019-02-17 07:41:22 +01:00
rlar 37c5813d68 bsim6.va, macro for hypsmooth, to avoid derivatives of this function 2019-02-17 07:41:22 +01:00
rlar fa13ee77d6 dev.c and inp2m.c, bsim6 is level 16 ?! 2019-02-17 07:41:21 +01:00
rlar f87b32962a r2_cmcguesstopology.c, r2_cmc.va, block local does not work 2019-02-17 07:41:21 +01:00
rlar 6777b43be5 fix $given and $param_given 2019-02-17 07:41:21 +01:00
rlar 951fc54139 ngspiceMODULE.hxx.xml, add BOLTZMANN and ELECTON_CHARGE 2019-02-17 07:41:21 +01:00
rlar c4ce6fa1f7 ngspiceMODULE.hxx.xml, add asinh etc derivative (fixme acosh atanh incomplete) 2019-02-17 07:41:20 +01:00
rlar 729ab44bd5 ngspiceMODULE.hxx.xml, $finish and test with r2_cmc.va 2019-02-17 07:41:20 +01:00
rlar f71926ad15 bsim6.va, work around body local vars (topology.c) 
again OPdependent related
 2019-02-17 07:41:20 +01:00
rlar 9e1f43e9d8 bsim6.va, split temporary variable T0 into two variables 
to avoid a dependency related problem in the xml files.
T0 and T0y, one of them have the OPdependent flag set
  which surpresses variable declarations to be emited.
 2019-02-17 07:41:20 +01:00
rlar c093420884 bsim6.va, split temporary variable T1 into two variables 
to avoid a dependency related problem in the xml files.
T1 and T1y, one of them have the OPdependent flag set
  which surpresses variable declarations to be emited.
 2019-02-17 07:41:19 +01:00
rlar 5b93bf1695 bsim6.va, split temporary variable T2 into two variables 
to avoid a dependency related problem in the xml files.
T2 and T2y, one of them have the OPdependent flag set
  which surpresses variable declarations to be emited.
 2019-02-17 07:41:19 +01:00
rlar 504ef5f5e5 bsim6.va, split temporary variable T3 into two variables 
to avoid a dependency related problem in the xml files.
T3 and T3y, one of them have the OPdependent flag set
  which surpresses variable declarations to be emited.
 2019-02-17 07:41:19 +01:00
Guilherme Brondani Torri e8da2ccbe1 avoid escape sequence %M, show hierarchical name 
* it will cause printf to fail
 2019-02-17 07:41:19 +01:00
rlar 83641704d2 bsim6.va, work around "case" 2019-02-17 07:41:18 +01:00
rlar 5f928354a2 bsim6.va, work around "for" (in guesstopology ?) 2019-02-17 07:41:18 +01:00
rlar 47a6e00291 scrub analoffunction.xml, (anti cpp) 2019-02-17 07:41:18 +01:00
Guilherme Brondani Torri 5a6b0cbf60 analogfunction, rename generated file from .cpp to .c 2019-02-17 07:41:17 +01:00
Guilherme Brondani Torri c7af29cd59 analogfunction, rename included file from [module]defs.h 2019-02-17 07:41:17 +01:00
rlar 45b362ca53 analogfunction.xml, name collission, rename function:getname and c:math_h 
these would shadow definitions in ngspiceVersion.xml
 2019-02-17 07:41:17 +01:00
rlar b1e757d89d extend "add analogfunction.xml from Qucs" 2019-02-17 07:41:17 +01:00
Guilherme Brondani Torri 54cb35f492 add analogfunction.xml from Qucs 
* This script creates a header and source [module].analogfuncion.[h.cpp]
  containing functions defined on the body of the Verilog-A model
 2019-02-17 07:41:16 +01:00
Guilherme Brondani Torri 7924d547ba add modulus symbol, multmod 2019-02-17 07:41:16 +01:00
rlar 99f6d4150c bsim6.va from bsim 6.1.1, see %bsim6.el 2019-02-17 07:41:16 +01:00
Guilherme Brondani Torri 062763f911 Add bsim6.va to build system 2019-02-17 07:41:16 +01:00
rlar 6ad8a801ba auxiliary my.mak files and %bsim6.el 2019-02-17 07:41:15 +01:00
Guilherme Brondani Torri 3d2bd1c6e1 register BSIM6 on adms ngspice interface 
$./autogen.sh --adms
...
[fatal..] bsim6: device not handled by the adms ngspice interface
[fatal..] see [../admst/ngspiceVersion.xml:2120]
 2019-02-17 07:41:15 +01:00
rlar 10219ace63 avoid unneccessairy diff noise (due to currentdate) in the adms generated files 2019-02-17 07:41:15 +01:00
dwarning 5fe1dca57a add resource file for fftw build 2019-02-16 19:05:29 +01:00
Holger Vogt 02bc314a54 Allow " around netnames for .plot and .print commands. 
This enables characters like - / + in netnames, e.g.
.print tran v("/jk-flip-flop-1/q")
 2019-02-11 23:11:08 +01:00
Holger Vogt 6a86e3347e correct the command name to 'setcs' 2019-02-06 23:11:48 +01:00
h_vogt 15542990bb command.c, inpcom.c, add command 'setcs': like command 'set', 
but case sensitive, and thus keeping upper or lower case
of subsequently following variable name and other letters.
 2019-02-06 22:31:05 +01:00
Holger Vogt 23402a01cc Add 'set stepsizelimit' also to spinit in 'make check' 2019-02-06 21:57:49 +01:00
dwarning e8ee1169b0 correct entry for vdmos bulk diode in acload 2019-02-06 18:31:12 +01:00
Holger Vogt daa5bdf203 -rm -> rm, re-enable 'make uninstall' 2019-02-04 20:53:25 +01:00
Holger Vogt ccb0319022 An example for non-convergence of the pll if the stepszelimit is removed. 
Adding a somewhat relaxed limit by TMAX in the tran command will speed
up the simulation by a factor of 1.5 without compromising the result.
 2019-02-02 09:46:07 +01:00
Holger Vogt c86f6265db relieve the step size limitation (formerly set to TSTEP in tran simulation). 
However not all examples will do without, thus the variable 'stepsizelimit'
is set in spinit. Unset it in .spiceinit to get the new behavior.
Of course then you might add the limit by setting TMAX in the tran command.
 2019-02-02 09:46:00 +01:00