Holger Vogt
|
925dc55a73
|
rename example file
|
2022-12-11 15:28:23 +01:00 |
Holger Vogt
|
ca1974ff37
|
Examples moved to folder /various
|
2022-12-11 15:28:01 +01:00 |
Holger Vogt
|
751019b447
|
Examples for d_pwm and d_osc
|
2022-12-11 15:27:42 +01:00 |
Holger Vogt
|
f13aa89626
|
Add new functions for operators x**y or x^y
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
|
2022-12-11 15:27:26 +01:00 |
Holger Vogt
|
d0f686727d
|
Add new functions for operators x**y or x^y
compatmode hs: x>0 pow(x, y), x<0 pow(x, round(y)), X=0 0
compatmode lt: x>0 pow(x, y), x<0 pow(x, y) if y is close to integer, else 0
|
2022-12-11 15:27:02 +01:00 |
Brian Taylor
|
9932a78e39
|
Add safety braces.
|
2022-12-11 15:26:42 +01:00 |
Brian Taylor
|
5726c9ff0b
|
Tidy up debug tracing code.
|
2022-12-11 15:26:16 +01:00 |
Brian Taylor
|
aa2f3b7bbb
|
Fix memory leaks.
|
2022-12-11 15:25:52 +01:00 |
Brian Taylor
|
4294f49968
|
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
|
2022-12-11 15:25:24 +01:00 |
Brian Taylor
|
cefa6b380c
|
When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary.
|
2022-12-11 15:25:00 +01:00 |
Brian Taylor
|
029df5a3d6
|
Check that the bparse gen_tab optimization loop finishes when no more improvements occur.
|
2022-12-11 15:24:35 +01:00 |
Holger Vogt
|
6af73bc97f
|
remove unused
|
2022-12-11 15:24:04 +01:00 |
Holger Vogt
|
d77e36dc1b
|
To find the nearest integer, use nearbyint(). trunc() has delivered
only one-sided answers.
|
2022-12-11 15:23:20 +01:00 |
Holger Vogt
|
47f2b7c6af
|
AlmostEqualUlps setting has been too strict: it failed in MINGW gcc.
3 --> 10
|
2022-12-11 15:22:54 +01:00 |
Holger Vogt
|
ba6ff75dab
|
Trim trailing spaces
|
2022-12-11 15:22:30 +01:00 |
Holger Vogt
|
f26c9146f5
|
Don't allocate memory for control array at every time step
Use loc instead, setting it up once during INIT
|
2022-12-11 15:22:01 +01:00 |
Holger Vogt
|
5d51107ff3
|
Add logicexp.c to fftw and shared project files
|
2022-12-11 15:21:30 +01:00 |
Brian Taylor
|
aff20b9db1
|
Remove asserts, replace fixed size lexer_buf.
|
2022-12-11 15:21:09 +01:00 |
Brian Taylor
|
d425beb557
|
Typo, 2 x1 subcircuits.
|
2022-12-11 15:20:49 +01:00 |
Brian Taylor
|
d54c1fc091
|
Add pindly tristate example. Cleanup error handling.
|
2022-12-11 15:20:27 +01:00 |
Brian Taylor
|
0627af435a
|
Remove most asserts.
|
2022-12-11 15:20:03 +01:00 |
Brian Taylor
|
b142be7fde
|
Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
|
2022-12-11 15:19:39 +01:00 |
Brian Taylor
|
4e76586b6b
|
Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
|
2022-12-11 15:19:17 +01:00 |
Brian Taylor
|
13c01abf0d
|
Fix a typo, add more comments.
|
2022-12-11 15:18:52 +01:00 |
Brian Taylor
|
68f0d49f58
|
Add support for TRISTATE: in PINDLY.
|
2022-12-11 15:18:32 +01:00 |
Brian Taylor
|
363179ce2f
|
Fix potential memory leak, clean out debug code.
|
2022-12-11 15:18:12 +01:00 |
Brian Taylor
|
499bef097e
|
Better estimates of rise/fall delays in PINDLYs with outputs separated by CASE.
|
2022-12-11 15:17:51 +01:00 |
Brian Taylor
|
a01edf2f36
|
Fix visualc compiler warnings.
|
2022-12-11 15:17:33 +01:00 |
Brian Taylor
|
22a3af8a1e
|
Improve delay estimates for pindly output buffers.
|
2022-12-11 15:17:17 +01:00 |
Brian Taylor
|
64c2c1ee05
|
Initial handling of PINDLY. Output buffers without rise/fall delay estimates.
|
2022-12-11 15:16:57 +01:00 |
Brian Taylor
|
62aab3885d
|
Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards.
|
2022-12-11 15:16:37 +01:00 |
Brian Taylor
|
7c699a599f
|
Fix potential memory leak.
|
2022-12-11 15:16:20 +01:00 |
Brian Taylor
|
a54aa4d1f7
|
Initial logicexp parser and gate generator.
|
2022-12-11 15:16:02 +01:00 |
Brian Taylor
|
4a904cdf18
|
Add drive 0/1 for $d_lo/$d_hi.
|
2022-12-11 15:15:44 +01:00 |
Holger Vogt
|
e47049f31a
|
Add STATIC_VAR_TABLE locdata
Add CALLBACK cm_d_pwm_callback
Reserve memory for x, y arrays only once during INIT
|
2022-12-11 15:15:22 +01:00 |
Brian Taylor
|
bda5d3f845
|
Distinguish between set/reset delays when possible.
|
2022-12-09 09:46:00 -08:00 |
Brian Taylor
|
afb5dcbffb
|
Make it optional to use zl/zh/lz/hz delays for utgate.
|
2022-12-08 17:15:34 -08:00 |
Brian Taylor
|
4054d4a580
|
Avoid unnecessary calculations for utgate.
|
2022-12-08 11:31:34 -08:00 |
Brian Taylor
|
74df1a1913
|
For utgate timing models, if hl/lh are not present use zl/zh/lz/hz to give a more accurate tristate delay.
|
2022-12-08 10:46:19 -08:00 |
Brian Taylor
|
a3950a6009
|
Merge branch 'pre-master' into bt_dev
|
2022-12-08 10:28:59 -08:00 |
Holger Vogt
|
d2833ac133
|
re-enable making old app nutmeg
|
2022-12-08 09:26:15 +01:00 |
Brian Taylor
|
d5cf918ce0
|
More conservative delay estimates for timing model type ugff.
|
2022-12-07 19:52:11 -08:00 |
Brian Taylor
|
29b39c94b2
|
Merge branch 'pre-master' into bt_dev
|
2022-12-07 11:19:47 -08:00 |
Brian Taylor
|
e7a85f95f0
|
For dff/jkff, obtain more conservative estimates for clk_delay, set_delay and reset_delay.
|
2022-12-07 11:12:22 -08:00 |
Brian Taylor
|
ee3c034b18
|
Merge branch 'pre-master' into bt_dev
|
2022-12-07 08:52:58 -08:00 |
Holger Vogt
|
23f72dd75c
|
Repair the broken --enable-oldapps option
|
2022-12-07 14:35:11 +01:00 |
Holger Vogt
|
622e7e1793
|
Fix previous commit
|
2022-12-04 11:12:54 +01:00 |
Holger Vogt
|
9d61bfdb7f
|
Example for configuring with --enable-shortcheck
|
2022-12-04 11:12:26 +01:00 |
Holger Vogt
|
1a83190d58
|
Add --enable-shortcheck as configure option
|
2022-12-04 11:12:03 +01:00 |
Holger Vogt
|
79f362980b
|
Add compile_cyg_make_short_check_64.sh as an example for --enable-shortcheck
|
2022-12-04 11:11:21 +01:00 |