0cae4f0b6c
special ngbehavior needed
2023-01-09 16:31:01 +01:00
c7fd3bcaee
Add example for 74f524.
2023-01-09 16:30:42 +01:00
4bcd4daf55
Rename projetc to OR (OR-gate)
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Add new path (absolute, so has to be modified by any user)
2022-12-27 14:22:07 +01:00
b639ebae44
Rename examples for ECL OR gate
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Simulate OR gate faster TSTEP 0.1n -> 0.3n
2022-12-27 14:21:24 +01:00
3e27e640b5
Missing renaming: osdi_win --> osdi_libs
2022-12-27 14:19:58 +01:00
4f73f18f6d
Remove
2022-12-27 14:19:18 +01:00
69660ad387
Move adder_common.inc to be available for all test files.
2022-12-27 14:18:54 +01:00
bb9469a03a
Rename test_osdi_libs to osdi_libs
2022-12-27 14:14:01 +01:00
96608abbe2
Update with Semimod download page
2022-12-27 14:13:27 +01:00
157200aa86
Rename test_osdi_win to test_osdi_libs
2022-12-27 14:13:02 +01:00
a211a90e5a
Mextram models: plotting with thicker lines
2022-12-27 14:12:41 +01:00
ac73e6f7b7
Update to the examples for osdi
2022-12-27 14:12:10 +01:00
d7bdfe1a20
Re-add optional selection of Berkeley model parameters.
2022-12-19 12:43:55 +01:00
5ec6543dbb
Add log plots
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Add sim vs. Temp.
Add y-labels
2022-12-19 12:43:27 +01:00
e28d3feee0
Remove unused variable debarr.
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Add another example.
2022-12-11 15:39:10 +01:00
45574cecb2
derivative inside of .func
2022-12-11 15:38:49 +01:00
89a48e7d73
simple example for derivative in B source
2022-12-11 15:38:37 +01:00
082ae1603e
add linewidth for graphs
2022-12-11 15:36:57 +01:00
058e7a34f8
tiny update, typos, font size
2022-12-11 15:36:42 +01:00
7ff8f3773f
Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
2022-12-11 15:34:33 +01:00
cd883d23d6
Examples for 74*568 behavioral subckts.
2022-12-11 15:33:53 +01:00
5324319edb
Move digital examples to new locations
2022-12-11 15:33:08 +01:00
925dc55a73
rename example file
2022-12-11 15:28:23 +01:00
ca1974ff37
Examples moved to folder /various
2022-12-11 15:28:01 +01:00
751019b447
Examples for d_pwm and d_osc
2022-12-11 15:27:42 +01:00
4294f49968
Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
2022-12-11 15:25:24 +01:00
d425beb557
Typo, 2 x1 subcircuits.
2022-12-11 15:20:49 +01:00
d54c1fc091
Add pindly tristate example. Cleanup error handling.
2022-12-11 15:20:27 +01:00
b142be7fde
Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
2022-12-11 15:19:39 +01:00
4e76586b6b
Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
2022-12-11 15:19:17 +01:00
43de22ec24
Update to the examples: enable plotting with option digitop
2022-10-24 17:05:34 +02:00
0aff89dc28
Example for URC distributed RC transmission line
2022-10-22 16:00:15 +02:00
ec6a902fb9
Fix a bug in simple diode, when ilimit is set, but not epsilon.
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Make model more similar to LTSPICE
Add an example
2022-10-08 16:50:38 +02:00
b212a49982
Add some automatic bridge examples, mostly using the bidirectional bridge.
2022-10-08 16:48:36 +02:00
cb42895dad
example for pwlts source code model
2022-10-07 13:39:33 +02:00
d39c60542d
Enable power measurement for W switch
2022-10-07 13:18:51 +02:00
fe8eb26aaf
Replace end-of-line comment delimiter $ by ;
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So to make it independent from compatibility switch selection.
2022-10-07 13:18:29 +02:00
f1eb8d3955
examples for .probe alli or .probe i(xx)
2022-10-07 13:17:55 +02:00
3dbfc934bb
set colors for grids and data
2022-10-07 13:17:06 +02:00
4706c3dea5
Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test.
2022-10-07 13:15:23 +02:00
e9b5a9a957
aswitch needs two input nodes because gd has been selected for input.
2022-10-07 13:13:38 +02:00
c8ed9590b7
Handle the case when control voltages on and off are equal.
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Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
2022-10-07 13:12:56 +02:00
5b0b328186
If a node name to be plotted ends by ':power', its type is set to POWER.
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Thus 'settype power nodename(s)' in the examples is no longer necessary.
2022-10-07 13:12:04 +02:00
2deefe1fbc
New tables for MOS devices
2022-10-07 13:11:18 +02:00
765d2e8a0e
Return data to input directory.
2022-10-07 13:10:51 +02:00
a69dd1bcde
Simplify the NMOS or PMOS selection by setting only one parameter
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'mostype'
ngspice-37+ is required.
2022-10-07 13:10:06 +02:00
7f38ce4ebb
Remove debug code.
2022-10-07 12:55:42 +02:00
112e47d0d3
This test is equivalent to examples/xspice/xspice_c3.cir and uses Pspice subckts for the divider and nand gate.
2022-10-07 12:53:03 +02:00
e8dfd16cb2
Add counter test. Check for usage of $d_lo, $d_hi, $d_nc usage with dff, jkff, dltch which will not translate to Xspice.
2022-10-07 12:52:39 +02:00
f7c519f149
All-digital U* device examples. No a/d or d/a interfaces on the subcircuits.
2022-10-07 12:52:20 +02:00
dwarning
Brian Taylor
Holger Vogt
h_vogt
Giles Atkinson