cc101495a5
Fix the xspice transmission_line examples.
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Also, cherry pick:
commit 87d09def9c
2025-07-29 10:57:55 +02:00
70ee0f8ef5
Add examples
2025-07-29 10:54:37 +02:00
d2ded9fa2c
Tiny modifications of SEE examples
2025-07-29 10:47:32 +02:00
3fb1ea1c39
Unix line endings
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rusage added
2025-07-29 10:46:39 +02:00
9d7db2166a
New example for seegen: CMOS comparator
2025-07-29 10:46:18 +02:00
07f8c3558b
Add a monitoring output the the seegen instance
2025-07-29 10:45:30 +02:00
b628032d7d
Add a generator for SEE (single event effects) pulses as a code model.
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To be used like
aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d')
see README.SEEgenerator for details
2025-07-29 10:39:58 +02:00
f73873c495
Enable expressions in a meas statement within a .control section, like
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meas tran yeval2 FIND v(2) WHEN v(1)= 0.9*v(2)
2025-07-29 10:37:59 +02:00
bba4046d55
Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,
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behaviour as before. Add similar pll-digital-iplot.cir as a
demonstration of iplot with analogue and digital nodes.
2025-05-24 11:28:42 +02:00
592b99d0ef
Rename pll-xspice.cir to shared-pll-xspice.cir to prepare for split.
2025-05-24 11:28:34 +02:00
a649514e87
Add an extended shared library test program with additional
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local commands to exercise the API.
2025-05-24 11:28:07 +02:00
2862d243d7
Add two simple Skywater PDK examples, inverter and ISCAS85 C7552
2025-05-24 11:13:43 +02:00
c7c85ecadc
Add co-simulation with VHDL, using the GHDL compiler and d_cosim.
2025-05-24 11:05:33 +02:00
4149edd146
Fix circuits so that gtkwave tests run on MacOS. Add encoder/decoder example.
2025-05-24 11:04:13 +02:00
00ad25fbc9
Fix d_process named pipes example. Use the correct gtkwave command for MacOS.
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The following is also required:
commit 527b8378e8
2025-05-24 11:03:52 +02:00
fd3827af40
Fix ordering of parameter definition and use.
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Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
2025-05-24 11:00:18 +02:00
edecf91437
options are not required
2025-05-24 10:58:45 +02:00
cef9d5b11c
iscas_stdcell.lib need geometry parameters, but is not used anyway, so commented out
2024-12-15 10:25:07 +01:00
fdbb62844c
Example for sending a text string over the subcircuit boundary.
2024-12-06 22:48:31 +01:00
c79b3501ef
Add note on compatibility mode psa
2024-12-06 22:41:31 +01:00
cf812da363
Try to clarify the mechanism of parameter substitution and add
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an example of substituting an XSPICE vector parameter.
2024-11-02 22:41:59 +01:00
d425d38c44
Old deprecated ADMS examples removed.
2024-11-02 22:38:17 +01:00
35968d1da6
Add additional examples of Verilog co-simulation and share the Verilog
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source and large parts of the example circuits between Verilator and
Icarus Verilog. Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
2024-11-02 22:30:32 +01:00
cab4f8d3d6
File encoding is now UTF-8
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change to letter µ
2024-11-02 22:22:22 +01:00
2c7f1e471b
vbic: rm obsolete regression test
2024-05-01 10:34:01 +02:00
bfb7798f97
measure example with expression evaluation
2024-03-29 17:12:40 +01:00
03a1010a65
Repeat loop requires plain number, transformed vector, or transformed variable
2024-03-19 17:05:10 +01:00
92b3a901c7
The values used in the foreach loop my be given by a vector
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(in addition to plain numbers or a list variable).
2024-03-19 16:41:27 +01:00
d92569742f
Add a transformer with parameters on the .subckt line
2024-01-24 10:11:44 +01:00
fb76eb5e12
Example for V/I sources, SFFM and AM
2024-01-08 13:24:01 +01:00
c46866d688
Fix some typos.
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Thanks to Brian for checking.
2023-12-18 20:13:06 +01:00
c69018fe82
Enable measurements with ?-sweep (v, i, temp, or res).
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Improve error messages.
Prevent crash is compüdata is not available.
Add to examples for measure failures.
2023-12-09 15:43:15 +01:00
1adee64224
Add scripts for running the paranoia tests in parallel on Linux with valgrind.
2023-12-04 15:12:15 +01:00
c18447f9f5
Add the support files for co-simulation with Verilog code
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compiled by Verilator. Also add script files to Visual Studio builds
that are already installed by the Makefile builds.
2023-11-27 20:55:59 +00:00
f6f7319792
Add null-pointer checks to some code that crashed when trying
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to .print results from a non-existent analysis. Also remove the
troublesome .plot and .print lines from two examples.
2023-11-09 12:07:31 +00:00
826cddb483
add examples for OSDI noise
2023-11-04 19:36:30 +01:00
f66e0bf2ac
implement osdi noise support
2023-11-04 19:36:30 +01:00
864ef7925c
Add notes on the structure and organization of an external d_process program.
2023-10-28 19:43:50 +02:00
5c6b9f03b5
Fix the zero count.
2023-10-28 19:43:41 +02:00
1f5f7ae439
Update d_process examples.
2023-10-28 19:43:36 +02:00
09f070f582
Error handling improvements in cfunc.mod. Ensure that d_process.h wiil always respond to version and interface checks sent from sendheader. This is needed so that the pipe reads in sendheader do not cause Windows to hang when the interface version and in/out counts do not match. This hang was the cause of errors not being reported and the Windows gui hanging. Startup and header checks are now detected in cm_d_process, and the simulator will run but with runtime errors since a d_process model cannot be completely instantiated after initial errors. It would be good to find a means of gracefully halting the simulation run.
2023-10-28 11:00:33 +02:00
4530cde8e2
Use Xspice cm_message_send to report errors rathen than printing to stderr and calling exit. When a d_process model has errors found in start(), sendheader(), and dprocess_exchangedata() these are reported, but if the model is run a SIGINT is raised. There must be a better way of stopping the simulator.
2023-10-28 11:00:18 +02:00
182764a894
Add examples/xspice/d_process.
2023-10-28 11:00:12 +02:00
046be0cdc8
Use the PSP103 model pspnqs103va (including nqs option)
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as this is the standard in the IHP Open PDK.
2023-10-27 23:25:42 +02:00
4b226bf11c
add output for all noise sources
2023-10-11 09:52:44 +02:00
77c4cb5452
new bipolar noise example
2023-10-11 09:52:10 +02:00
f2247a3c6f
Use sparse, as KLU will fail.
2023-09-10 13:43:09 +02:00
716bb0a6bc
Add plot for inverter gain
2023-08-30 14:23:25 +02:00
161ace44da
Restore the original model parameters.
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Add information on its source.
2023-08-28 12:11:20 +02:00
b08eb2266a
Added initial KLU support for node collapsing
2023-08-16 11:14:24 +02:00
Brian Taylor
Vadim Kuznetsov
Holger Vogt
Giles Atkinson
dwarning
dwarning
Pascal Kuthe
Francesco Lannutti