Brian Taylor
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048dcb3bf1
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Go back to before previous merge.
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2024-04-03 17:12:57 +02:00 |
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Brian Taylor
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db4476d22b
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Remove unnecessary #include.
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2024-04-03 17:12:50 +02:00 |
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Brian Taylor
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367cdf5708
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Add variable ps_scan_gates_optimize (default 1). If < 1, then turn off the optimizations in scan_gates.
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2024-04-03 17:12:43 +02:00 |
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Brian Taylor
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c3fa6328a1
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Fix bug in the LOGICEXP scan_gates optimizer. Some gates with an inverting output were generated with bad logic which gave incorrect simulation results.
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2024-03-29 17:29:49 +01:00 |
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Brian Taylor
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715ce8c809
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Return correct error statuses. Detect another illegally placed gate operator in an infix expression.
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2024-03-15 21:53:13 +01:00 |
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Brian Taylor
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14bf034f28
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The lexer incorrectly treats a single '_' '-' '/' as an identifier. The counter used for tmp__ names should be incremented after use. The infix_to_postfix converter now has more checks for invalid infix expressions in LOGICEXP constructs. Without these checks the evaluation of the generated postfix could silently create bad gates which would load but simulate incorrectly. All MicroCap and PSpice libraries and QEI.cir pass their tests.
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2024-03-11 22:25:48 +01:00 |
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Brian Taylor
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ae8e423d97
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Add WARNINGs when there are potential name collisions, and identify the possible name.
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2024-03-11 22:25:39 +01:00 |
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Brian Taylor
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4c983e9133
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Remove old dead code.
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2024-02-23 14:06:39 +01:00 |
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Brian Taylor
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8788ce3504
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Add check for a trailing } in a logicexp statement.
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2024-02-23 14:06:28 +01:00 |
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Brian Taylor
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826401f6a4
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Add error detection and reporting for invalid infix expressions.
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2024-02-23 14:06:17 +01:00 |
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Brian Taylor
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e01290c9a2
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Replace the logicexp parser with infix to postfix translation followed by evaluating the postfix. logicexp.c is now shorter and easier to understand and maintain. Also, operator precedence expression parsing conforms to the PSPICE rules. Thus, a & b | c is understood to mean (a & b) | c, for example.
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2024-02-13 10:11:28 +01:00 |
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Brian Taylor
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a70297e87a
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Several PSPICE 9.1 evaluation digital libraries contain timing .model statements at the global level for subckts with U* instances that reference those models. By specifying "set ps_global_tmodels=1" in .spiceinit an extra pass inside u_instances() will collect those global timing models for use in subckts. Report errors detected when ngspice parses a LOGICEXP but has not added support for operator precendence. Include a hint of how to fix those errors by inserting parentheses. This error only occurs in 10 of 585 cases in the libraries. Note that inpcompat.c has been saved as a unix filetype.
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2024-01-17 14:15:07 +01:00 |
dwarning
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4368790c5d
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remove compiler warning wrt. prototypes
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2023-09-11 14:50:27 +02:00 |
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Brian Taylor
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492bb64d92
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By default, use the shortest typical delay estimate. This makes the digi_74LS90_74LS42.cir testcase for bug641 behave almost the same as MicroCap 12. In ngspice and MicroCap, the only signal with a glitch is not_y8. The other not_* signals look the same. Setting ps_use_mntymx in .spiceinit will change the delay estimates. See the function set_u_devices_info in src/frontend/udevices.c for the various settings of ps_use_mntymx.
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2023-09-09 23:22:06 +02:00 |
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Brian Taylor
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4d8b105b86
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Simplify expression nesting depth.
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2023-07-15 11:34:09 +02:00 |
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Brian Taylor
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8c69ada5b5
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The logicexp example in the PSpice ref. manual has a name with a '+' character (LCN+4). Update lexer_scan.
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2023-03-22 14:26:43 +01:00 |
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Brian Taylor
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40a540a2ff
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Add inertial_delay=true to .model statements generated when U* instances in PSpice library subckts are translated to Xspice. Any other Xspice A* digital instances might have different inertial_delay settings in their models, so potentially there could be a mixture of delay types. For example, if a user wishes to model a DLYLINE using a d_buffer with inertial_delay=false and equal rise/fall delays.
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2023-03-22 14:26:18 +01:00 |
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Brian Taylor
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164db58404
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The intent now is to rely on a variable setting in .spiceinit to control the use of inertial delay XSPICE digital models. This will apply to U* instances in subcircuits which are translated to XSPICE.
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2023-03-22 14:25:51 +01:00 |
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Brian Taylor
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4111aaf110
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When logicexp has a ugate timing model other than d0_gate, use its delays for an inverter or buffer.
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2023-03-18 14:36:45 +01:00 |
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Brian Taylor
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3a76a1ef52
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Prepare for inertial_delay model parameter.
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2023-03-18 14:36:17 +01:00 |
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Brian Taylor
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8dd16feee4
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Use dstrings where fixed size char buffers should not have been used.
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2023-03-18 14:32:31 +01:00 |
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Brian Taylor
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3365fd4309
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Remove dead code.
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2023-03-18 14:32:19 +01:00 |
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Brian Taylor
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56d0c72924
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Add port directions when logicexp or pindly are present.
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2023-02-01 17:39:37 +01:00 |
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Brian Taylor
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dcfe4e7134
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ERROR messages should be printed to stderr.
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2023-01-15 13:37:42 +01:00 |
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Brian Taylor
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a76f8d5149
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Fix some comments.
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2023-01-09 16:33:25 +01:00 |
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Brian Taylor
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6117836d01
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Ensure that amatch output is not binary data.
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2023-01-09 16:30:22 +01:00 |
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Brian Taylor
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5e6452099e
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Return errors from f_logicexp and f_pindly without calling exit.
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2023-01-09 16:29:08 +01:00 |
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Brian Taylor
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0a3cdf8e3a
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Add more error checks for f_logicexp and f_pindly.
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2023-01-09 16:28:43 +01:00 |
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Brian Taylor
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fe52771aff
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Remove the old inverter code.
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2022-12-27 14:21:05 +01:00 |
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Brian Taylor
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3578deda80
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Refactor new_gen_output_models.
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2022-12-27 14:20:43 +01:00 |
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Brian Taylor
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929d1f5190
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Added xor/xnor for logicexp timing models.
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2022-12-11 15:34:56 +01:00 |
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Brian Taylor
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7ff8f3773f
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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2022-12-11 15:34:33 +01:00 |
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Brian Taylor
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1511214874
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Add more debug instrumentation.
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2022-12-11 15:31:09 +01:00 |
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Brian Taylor
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fe733a8ca2
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Use tilde '~' inputs instead of creating inverters.
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2022-12-11 15:30:41 +01:00 |
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Brian Taylor
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9932a78e39
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Add safety braces.
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2022-12-11 15:26:42 +01:00 |
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Brian Taylor
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5726c9ff0b
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Tidy up debug tracing code.
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2022-12-11 15:26:16 +01:00 |
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Brian Taylor
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aa2f3b7bbb
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Fix memory leaks.
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2022-12-11 15:25:52 +01:00 |
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Brian Taylor
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4294f49968
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Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
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2022-12-11 15:25:24 +01:00 |
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Brian Taylor
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cefa6b380c
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When the gen_tab has only one entry, do not call optimize_gen_tab, it is not necessary.
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2022-12-11 15:25:00 +01:00 |
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Brian Taylor
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029df5a3d6
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Check that the bparse gen_tab optimization loop finishes when no more improvements occur.
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2022-12-11 15:24:35 +01:00 |
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Brian Taylor
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aff20b9db1
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Remove asserts, replace fixed size lexer_buf.
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2022-12-11 15:21:09 +01:00 |
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Brian Taylor
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d54c1fc091
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Add pindly tristate example. Cleanup error handling.
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2022-12-11 15:20:27 +01:00 |
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Brian Taylor
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0627af435a
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Remove most asserts.
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2022-12-11 15:20:03 +01:00 |
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Brian Taylor
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b142be7fde
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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2022-12-11 15:19:39 +01:00 |
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Brian Taylor
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4e76586b6b
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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2022-12-11 15:19:17 +01:00 |
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Brian Taylor
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13c01abf0d
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Fix a typo, add more comments.
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2022-12-11 15:18:52 +01:00 |
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Brian Taylor
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68f0d49f58
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Add support for TRISTATE: in PINDLY.
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2022-12-11 15:18:32 +01:00 |
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Brian Taylor
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363179ce2f
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Fix potential memory leak, clean out debug code.
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2022-12-11 15:18:12 +01:00 |
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Brian Taylor
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499bef097e
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Better estimates of rise/fall delays in PINDLYs with outputs separated by CASE.
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2022-12-11 15:17:51 +01:00 |
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Brian Taylor
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a01edf2f36
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Fix visualc compiler warnings.
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2022-12-11 15:17:33 +01:00 |