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390 Commits

Author SHA1 Message Date
Holger Vogt d36c4b8772 Remove bulk simulation netlist from files 
needing a .control section.
 2023-01-28 17:02:13 +01:00
Holger Vogt 8c98b70e45 Add input file dedicated to batch mode, 
to be run with
ngspice -b -r inv.out bsimbulk_inverter_bach.sp
 2023-01-28 17:01:53 +01:00
Holger Vogt 512bcf6095 Remove unused folder 2023-01-28 17:01:37 +01:00
Holger Vogt dbdbcf95c2 BSIMBULK example with locally adding osdi models 
by using the 'pre_osdi' command in a .control section
 2023-01-28 17:01:22 +01:00
Holger Vogt b9eef23eed Update the example structure for OSDI/OpenVAF: 
all compiled models into lib/ngspice
spinit updated to load the models via command 'osdi'
local calls with 'pre_osdi' commanted out.
 2023-01-27 16:08:17 +01:00
Holger Vogt 5bd45eeb87 The Roessler Attractor examples has been provided by 
Giles Atkinson, of course
 2023-01-24 16:29:50 +01:00
Holger Vogt 16c7c407d4 Nice looking Roessler Attractor 
provided by A. Gillespie
 2023-01-24 15:17:45 +01:00
Holger Vogt cb5f9e9bdc MOS example files updated and moved to its own directory 2023-01-24 15:17:31 +01:00
Holger Vogt af9f25e985 Various filter examples using Laplace expression x_fer 2023-01-20 15:07:37 +01:00
Giles Atkinson bf580abf69 Add a simple example of using string-valued parameters. 2023-01-09 16:33:53 +01:00
Holger Vogt 01c211339c Rename example file 2023-01-09 16:33:38 +01:00
Brian Taylor 4936fa2b1d Add serial load to 74f524 example. 2023-01-09 16:33:10 +01:00
dwarning 0cae4f0b6c special ngbehavior needed 2023-01-09 16:31:01 +01:00
Brian Taylor c7fd3bcaee Add example for 74f524. 2023-01-09 16:30:42 +01:00
Holger Vogt 4bcd4daf55 Rename projetc to OR (OR-gate) 
Add new path (absolute, so has to be modified by any user)
 2022-12-27 14:22:07 +01:00
Holger Vogt b639ebae44 Rename examples for ECL OR gate 
Simulate OR gate faster TSTEP 0.1n -> 0.3n
 2022-12-27 14:21:24 +01:00
Holger Vogt 3e27e640b5 Missing renaming: osdi_win --> osdi_libs 2022-12-27 14:19:58 +01:00
Holger Vogt 4f73f18f6d Remove 2022-12-27 14:19:18 +01:00
Holger Vogt 69660ad387 Move adder_common.inc to be available for all test files. 2022-12-27 14:18:54 +01:00
Holger Vogt bb9469a03a Rename test_osdi_libs to osdi_libs 2022-12-27 14:14:01 +01:00
Holger Vogt 96608abbe2 Update with Semimod download page 2022-12-27 14:13:27 +01:00
Holger Vogt 157200aa86 Rename test_osdi_win to test_osdi_libs 2022-12-27 14:13:02 +01:00
Holger Vogt a211a90e5a Mextram models: plotting with thicker lines 2022-12-27 14:12:41 +01:00
Holger Vogt ac73e6f7b7 Update to the examples for osdi 2022-12-27 14:12:10 +01:00
Holger Vogt d7bdfe1a20 Re-add optional selection of Berkeley model parameters. 2022-12-19 12:43:55 +01:00
h_vogt 5ec6543dbb Add log plots 
Add sim vs. Temp.
Add y-labels
 2022-12-19 12:43:27 +01:00
Holger Vogt e28d3feee0 Remove unused variable debarr. 
Add another example.
 2022-12-11 15:39:10 +01:00
Holger Vogt 45574cecb2 derivative inside of .func 2022-12-11 15:38:49 +01:00
Holger Vogt 89a48e7d73 simple example for derivative in B source 2022-12-11 15:38:37 +01:00
Holger Vogt 082ae1603e add linewidth for graphs 2022-12-11 15:36:57 +01:00
Holger Vogt 058e7a34f8 tiny update, typos, font size 2022-12-11 15:36:42 +01:00
Brian Taylor 7ff8f3773f Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file. 2022-12-11 15:34:33 +01:00
Brian Taylor cd883d23d6 Examples for 74*568 behavioral subckts. 2022-12-11 15:33:53 +01:00
Holger Vogt 5324319edb Move digital examples to new locations 2022-12-11 15:33:08 +01:00
Holger Vogt 925dc55a73 rename example file 2022-12-11 15:28:23 +01:00
Holger Vogt ca1974ff37 Examples moved to folder /various 2022-12-11 15:28:01 +01:00
Holger Vogt 751019b447 Examples for d_pwm and d_osc 2022-12-11 15:27:42 +01:00
Brian Taylor 4294f49968 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented. 2022-12-11 15:25:24 +01:00
Brian Taylor d425beb557 Typo, 2 x1 subcircuits. 2022-12-11 15:20:49 +01:00
Brian Taylor d54c1fc091 Add pindly tristate example. Cleanup error handling. 2022-12-11 15:20:27 +01:00
Brian Taylor b142be7fde Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE. 2022-12-11 15:19:39 +01:00
Brian Taylor 4e76586b6b Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly. 2022-12-11 15:19:17 +01:00
Holger Vogt 43de22ec24 Update to the examples: enable plotting with option digitop 2022-10-24 17:05:34 +02:00
Holger Vogt 0aff89dc28 Example for URC distributed RC transmission line 2022-10-22 16:00:15 +02:00
Holger Vogt ec6a902fb9 Fix a bug in simple diode, when ilimit is set, but not epsilon. 
Make model more similar to LTSPICE
Add an example
 2022-10-08 16:50:38 +02:00
Giles Atkinson b212a49982 Add some automatic bridge examples, mostly using the bidirectional bridge. 2022-10-08 16:48:36 +02:00
Holger Vogt cb42895dad example for pwlts source code model 2022-10-07 13:39:33 +02:00
Holger Vogt d39c60542d Enable power measurement for W switch 2022-10-07 13:18:51 +02:00
Holger Vogt fe8eb26aaf Replace end-of-line comment delimiter $ by ; 
So to make it independent from compatibility switch selection.
 2022-10-07 13:18:29 +02:00
Holger Vogt f1eb8d3955 examples for .probe alli or .probe i(xx) 2022-10-07 13:17:55 +02:00