Tim Edwards
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6ac19b03a3
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examples/xspice/d_lut/mult4bit.spi, example for d_lut and d_genlut
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2017-05-01 22:11:50 +02:00 |
h_vogt
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30aa5ec0b7
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examples/xspice/table, examples for the table2d and table3d code models
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2017-04-30 17:01:07 +02:00 |
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h_vogt
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fb90bebcab
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example for .options interp (reduces memory, speeds up plotting)
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2014-02-01 14:31:38 +01:00 |
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h_vogt
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5ed51c2668
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example input file as cited in manual
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2012-10-21 11:50:23 +02:00 |
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h_vogt
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177964b4a6
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XSPICE example: delta-sigma converter
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2012-08-14 23:06:34 +02:00 |
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h_vogt
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5d0c3182d3
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add BSIM3 model parameters for loop filer with transistor charge pump
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2012-08-05 20:15:53 +02:00 |
dwarning
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96dd397251
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correct the plot output
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2012-08-05 12:06:11 +02:00 |
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h_vogt
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19a67fb7c5
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pll: just include one of the two vco available
(avoid a bug which has been removed only recently)
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2012-08-04 00:22:25 +02:00 |
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h_vogt
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a0db6f0ccd
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update to XSPICE phase-locked loop example
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2012-08-03 23:22:54 +02:00 |
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h_vogt
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6cd13e0475
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pll-xspice-fstep.cir: pll with ref frequency steps
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2012-07-31 18:05:10 +02:00 |
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h_vogt
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c31fc334f6
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pll-xspice.cir: save command added
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2012-07-31 17:31:28 +02:00 |
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h_vogt
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c0b5a78097
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new XSPICE example: use trtol=1
less ripple, but longer simulation time
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2012-07-30 00:01:56 +02:00 |
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h_vogt
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85ece25a3a
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new XSPICE example: mixed mode pll circuit
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2012-07-29 13:52:23 +02:00 |
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h_vogt
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926a7b338c
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'filesource' test
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2011-06-23 19:56:46 +00:00 |
rlar
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b1f6da536a
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whitespace cleanup, add missing trailing newlines
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2010-09-07 19:04:20 +00:00 |
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h_vogt
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adc911d412
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xspice examples
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2010-05-14 20:33:20 +00:00 |
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h_vogt
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57097463ee
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xspice examples
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2009-12-21 18:23:55 +00:00 |