Add some description, correct minor bugs.

This commit is contained in:
Holger Vogt
2018-09-02 18:05:06 +02:00
parent 12c864fb5a
commit 925cb49ff2
5 changed files with 53 additions and 17 deletions
+20 -5
View File
@@ -1,4 +1,17 @@
** NMOSFET: table generator with BSIM4 2D (Vdrain, Vgate)
** NMOSFET: table generator with BSIM4 3D (Vdrain, Vgate, Vbulk)
* This file may be run by 'ngspice table-generator-b4-3d.sp'
* It will generate a 3D data table by simulating the MOS drain current
* as function of drain and gate voltages. The simulation uses
* the ngspice BSIM4.6.1 MOS model and Berkeley model parameters.
* This table is an input file for the XSPICE 3D table model.
* You have to select NMOS or PMOS by manually editing this file: currently
* NMOS is selected. For PMOS change '*' in column 1
* for CSPARAM, m1, outfile, echo *table...
* In addition you may change the step sizes vdstep vgstep vbstep in CSPARAM
* to obtain the required resolution for the data.
* These tables will contain pure dc data. For transient simulation you may
* need to add some capacitors to the device model for a 'real world' simulation.
*NMOS
.csparam vdstart=-0.1
.csparam vdstop=1.8
@@ -22,8 +35,8 @@
*.csparam vbstep=0.2
** Circuit Description **
m1 2 1 3 4 n1 L=0.13u W=10.0u rgeoMod=1
*m1 2 1 3 4 p1 L=0.13u W=10.0u rgeoMod=1
m1 2 1 3 4 nbsim4 L=0.13u W=10.0u rgeoMod=1
*m1 2 1 3 4 pbsim4 L=0.13u W=10.0u rgeoMod=1
vgs 1 0 1.8
vds 2 0 1.8
vss 3 0 0
@@ -32,9 +45,11 @@ vbs 4 0 0
.control
** output file **
set outfile = "bsim4n-3d-1.table"
*set outfile = "bsim4p-3d-1.table"
save i(vss)
echo * 3D table for nmos bsim 4 > $outfile
*echo * 3D table for nmos bsim 4 > $outfile
let xcount = floor((vdstop-vdstart)/vdstep) + 1
let ycount = floor((vgstop-vgstart)/vgstep) + 1
@@ -101,7 +116,7 @@ while lcz < zcount
end
.endc
.include ./modelcards/modelcard.pmos
.include ./modelcards/modelcard.nmos
.include ./modelcards/modelcard.pmos
.end