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Fix Bug #630 - "pwl if r=last time, simulation never ends". 

Allowing a PWL repeat to start at the last time-point makes no sense.
This commit is contained in:
Giles Atkinson 2023-05-14 17:18:26 +01:00 committed by Holger Vogt
parent f4f2f41940
commit 2db6b529f2
1 changed files with 1 additions and 1 deletions
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2
src/spicelib/devices/vsrc/vsrcpar.c
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@ -140,7 +140,7 @@ VSRCparam(int param, IFvalue *value, GENinstance *inst, IFvalue *select)
}
end_time = *(here->VSRCcoeffs + here->VSRCfunctionOrder-2);
if ( here->VSRCr > end_time ) {
if ( here->VSRCr >= end_time ) {
fprintf(stderr, "ERROR: repeat start time value %g for pwl voltage source must be smaller than final time point given!\n", here->VSRCr );
return ( E_PARMVAL );
}