From 2db6b529f2656a61883f07a50c7a0b51e0cda2d8 Mon Sep 17 00:00:00 2001
From: Giles Atkinson <“gatk555@gmail.com”>
Date: Sun, 14 May 2023 17:18:26 +0100
Subject: [PATCH] Fix Bug #630 - "pwl if r=last time, simulation never ends".
 Allowing a PWL repeat to start at the last time-point makes no sense.

---
 src/spicelib/devices/vsrc/vsrcpar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/spicelib/devices/vsrc/vsrcpar.c b/src/spicelib/devices/vsrc/vsrcpar.c
index 19686293f..72738cd31 100644
--- a/src/spicelib/devices/vsrc/vsrcpar.c
+++ b/src/spicelib/devices/vsrc/vsrcpar.c
@@ -140,7 +140,7 @@ VSRCparam(int param, IFvalue *value, GENinstance *inst, IFvalue *select)
             }
 
             end_time     = *(here->VSRCcoeffs + here->VSRCfunctionOrder-2);
-            if ( here->VSRCr > end_time ) {
+            if ( here->VSRCr >= end_time ) {
               fprintf(stderr, "ERROR: repeat start time value %g for pwl voltage source must be smaller than final time point given!\n", here->VSRCr );
               return ( E_PARMVAL );
             }