The chip used in tangnano4k does not have such pins, but we call the
function anyway in the expectation of other chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* both instances of the new PLLVR type are supported;
* primitive placement is optimized for the use of dedicated PLL clock
pins;
* all 4 outputs of each primitive can use the clock nets (only 5 lines
in total at the same time so far).
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Each DSP block contains two slices, and each slice contains multiple
MULT18X18D and ALU54B units. Each unit configures each register to use
any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are
connected per unit (so for example, two MULTs in the same block could
connect their CLK0s to different external signals). However, the
hardware only has one actual port per block, so it's required that
all CLK0 signals within a block are the same.
Because the packer is in general allowed to combine two unrelated units
into one block, it may end up combining units that use different signals
for the same port, which would eventually have caused a router failure.
This commit adds validity checks which ensure only unique signals are
used per block, and adds remapping so that conflicting signals are
automatically reassigned when possible and required.
The dedicated router for clock wires now understands not only the IO
pins but also the rPLL outputs as clock sources.
This simple router sets an optimal route, so it is now the default
router. It can be disabled with the --disable-globals command line flag
if desired, but this is not recommended due to possible clock skew.
Still for GW1N-4C there is no good router for clock wires as there
external quartz resonator is connected via PLL.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
And do a full enumeration when searching for a delay because it is not
yet clear whether the orderliness of the vector is guaranteed.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A large number of global variables are not suitable for WASM, so
completely disable the graphics part where the main array of them is
used. For other architectures GUI is still possible.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When a single primitive occupies several cells, care must be taken when
manipulating the parameters of that primitive: when creating cells, each
cell must receive a copy of all the parameters and not modify them
unnecessarily. That is, if possible, it is better to make all parameter
changes before dividing the primitive into cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When there is a constraint conflict while placing IOs, the user gets an
error message such as
ERROR: Bel 'X0/Y27/io1' of type 'SB_IO' is not valid for cell 'my_pin' of type 'SB_IO'
While this identifies the problematic cell, it does not explain why
there is a problem. Add some verbose messages to allow users to
determine where the problem is. This can result in something like
Info: Net '$PACKER_VCC_NET' for cell 'my_pin' conflicts with net 'ce' for 'ce_pin'
which provides something actionable.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Until a comprehensive clock router is developed, the order in which
private cases are handled is important.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
gatecat
YRabbit
Adam Greig
Miodrag Milanovic
Arjen Roodselaar
Sean Anderson