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2,436 Commits 29 Branches 10 Tags 22 MiB
Commit Graph

180 Commits

Author SHA1 Message Date
Miodrag Milanovic 796d648995 Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui 2019-12-28 13:54:06 +01:00
Miodrag Milanovic 436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic 19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic 7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic 275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic 401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic 76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic 74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah 475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah 36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic 49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic 0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah 9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah 9f9920f92b ecp5: Add full part name to bitstream header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 14:36:20 +01:00
David Shah 78f86ce67a ecp5: Add GSR/SGSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:14:41 +01:00
David Shah c70f87e4c5
Merge pull request #309 from YosysHQ/dsptiming 
ecp5: Conservative analysis of comb DSP timing
 2019-08-09 10:27:15 +01:00
David Shah 661237eb64 ecp5: Add --out-of-context for building hard macros 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:22:47 +01:00
David Shah ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah 2da41a66c7 ecp5: Conservative analysis of comb DSP timing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 15:09:54 +01:00
Miodrag Milanovic ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
David Shah df8688c227 ecp5: Delay tweaking for lower speed grades 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:55:23 +01:00
David Shah 7ae64b9477 ecp5: Reduce cfg.criticalityExponent for now 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:20:46 +01:00
Miodrag Milanovic 36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic 78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic 54175f9187 No need for this one 2019-06-07 13:24:16 +02:00