8 Commits

Author	SHA1	Message	Date
Eddie Hung	fa3d366ddb	Add missing operator needed by router_improve	2018-11-13 10:10:57 -08:00
Eddie Hung	ca7eef26ac	Wires now encapsulate segments	2018-09-02 16:57:11 -07:00
Eddie Hung	17918b5992	Fix for multiple id_SLICE_LUT6 per actual SLICE	2018-08-17 23:05:12 -07:00
Eddie Hung	7b15569c69	Use general pin names for QUARTER_SLICE	2018-08-12 20:29:04 -07:00
Eddie Hung	56b7299cca	{SLICEL,SLICEM} -> QUARTER_SLICE	2018-08-12 20:21:03 -07:00
Eddie Hung	57c273898c	Finishes placement now	2018-08-11 22:24:13 -07:00
Eddie Hung	8cddc49abc	Starts placement onto all Xilinx sites	2018-08-11 18:52:48 -07:00
Eddie Hung	d53658a079	Copy ice40 into xc7	2018-08-11 14:35:49 -07:00