10 Commits

Include renames

Author	SHA1	Message	Date
gatecat	073bb87efb	clangformat ... Signed-off-by: gatecat <[email protected]>	2026-09-28 13:22:17 +02:00
gatecat	3edea68ef3	Tidy up pin constraint handling for singleton vectors ... Signed-off-by: gatecat <[email protected]>	2026-09-21 10:01:14 +02:00
gatecat	9b51c6e337	clangformat ... Signed-off-by: gatecat <[email protected]>	2024-09-30 14:51:33 +02:00
Rowan Goemans	86106cb49a	timing: integrate c2c delays and cleanup code	2024-09-24 08:57:21 +02:00
Rowan Goemans	fc3b2de8da	timing: Add clock skew to arrival and required time	2024-09-24 08:57:21 +02:00
rowanG077	914999673c	Rip out budgets	2023-06-20 10:57:10 +02:00
gatecat	ea925f39fb	archapi: Add getArcDelayOverride ... Signed-off-by: gatecat <[email protected]>	2023-05-17 09:54:14 +01:00
gatecat	6079326633	context: Add getNetinfoRouteDelayQuad ... Signed-off-by: gatecat <[email protected]>	2023-01-18 16:28:33 +01:00
gatecat	09e388f453	netlist: Add PseudoCell API ... When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.	2022-07-08 14:30:57 +02:00
gatecat	49f178ed94	Split up common into kernel,place,route ... Signed-off-by: gatecat <[email protected]>	2022-04-08 13:42:54 +01:00