15 Commits

Author	SHA1	Message	Date
gatecat	579b98c596	Use hashlib for core netlist structures ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-06-02 14:27:56 +01:00
gatecat	eb2265a2bf	mistral: Make RBF compression optional ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-30 15:50:12 +01:00
gatecat	9d7f90dd89	mistral: Add MISTRAL_CLKBUF cell type ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 21:28:48 +01:00
gatecat	9221acc9e2	mistral: Fix ENA and ACLR bitstream generation ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	87ebada258	mistral: Fix EF_SEL and BTO_DIS ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	8bc9732d49	mistral: PKREG bits appear to be mirrored within a half? ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	b29fa1d24c	mistral: FF&CLKBUF fixes, part 1 ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	66b3a192f8	mistral: First pass at FF and CLKBUF bitgen ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	09a867310b	mistral: Carry fixes ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	3d1bb4f1b2	mistral: Carry debugging ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	2f2fde7e6c	mistral: Write arith mode to bitstream (not yet functional) ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	bacba274a2	mistral: Write LUT inits ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	d1f635242d	mistral: Add some IO configuration ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	dea4c6f53f	mistral: Setting some more boilerplate bits ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00
gatecat	27eb3be7da	mistral: Add stub RBF generation ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-05-15 14:54:33 +01:00