6387a3d33e
ice40: Only create padin gbuf for PLLs if global output actually used
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-17 14:06:23 +02:00
9dd68aa0e2
ice40: Take placed SB_GBs into account when placing PLLs
...
Because the PLLs drive global networks, we need to account for
already existing and placed SB_GBs when trying to place/pack them.
Theses can be user instanciated SB_GBs with BEL attribute, or
SB_GB_IOs that got converted during the IO packing.
This patch assumes that:
- If a PLL is used the output A global network is always used, even
if there is no connection to the global output pin
- If a PLL with a singe output is used, then the B output global
network is still free to be used by whatever.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-16 10:12:28 +02:00
6cb4e2e83b
ice40/pack: During IO packing, remove any unused input connection
...
This is mostly for the benefit of PLL placement because the D_IN_x
ports are used for other purposes when PLL is enabled so we need to
make sure nothing is connected there already. (even an unused net is
too much)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-11 13:52:23 +02:00
d27ec2cd15
ice40: Don't constrain to a PLL bel that has already been used
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Fixes #258
Signed-off-by: David Shah <dave@ds0.me>
2019-04-01 12:25:32 +01:00
d401e3e1a0
ice40: Add support for SB_I2C and SB_SPI
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-25 23:48:59 +01:00
02ae21d8fc
Add --placer option and refactor placer selection
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 11:10:20 +00:00
bd12c0a486
HeAP: Add PlacerHeapCfg
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
7142db28a8
HeAP: Make HeAP placer optional
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A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.
Default for the iCE40 is SA placer, with --heap-placer to use HeAP
Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.
Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
ea56dc9d08
HeAP: Add TAUCS wrapper and integration
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
1780f42b9a
ice40: Add examples folder including floorplan example
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
493d6c3fb9
Add Python helper functions for floorplanning
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 10:31:54 +00:00
1060810d7a
ice40: Fix u4k in external chipdb mode.
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Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
2019-03-19 15:23:43 +01:00
e87fb69665
ice40: u4k merge fix
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-25 11:36:12 +00:00
7a5699891a
Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires
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ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
2019-02-25 08:20:32 +00:00
7044f56246
ice40: support u4k
2019-02-23 17:39:20 +01:00
a05f6b261e
ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-21 20:34:23 +00:00
a7ea3f58e3
ice40: Fix timing class of 'padin' GB outputs
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-20 21:23:43 +00:00
c52202233a
Merge branch 'master' into mmaped_chipdb
2019-02-12 18:53:20 +01:00
8b0af0e48d
Fix according to comments on PR
2019-02-10 08:33:52 +01:00
054be887ae
ice40: PLLs can't conflict with themselves
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Fixes error building testcase from #145
Signed-off-by: David Shah <dave@ds0.me>
2019-02-09 19:27:52 +00:00
73f200fe74
Load chipdb from filesystem as option
2019-02-09 13:34:57 +01:00
170bf8a5ec
ice40: Don't create PLLOUT_B buffer for single-output PLL variants
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-09 10:41:22 +00:00
6d664046d3
Merge pull request #220 from YosysHQ/coi3
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ice40: Add budget override for CO->I3 path
2019-01-29 11:22:31 -08:00
77bb5ea63a
[ice40] Refactor Arch::getBudgetOverride()
2019-01-29 10:43:14 -08:00
cc53c312de
timing: Path related fixes
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-27 16:45:37 +00:00
f4d8a25fb7
ice40: Add budget override for CO->I3 path
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-27 14:43:10 +00:00
265fa1be16
Merge pull request #211 from smunaut/ice40_ram_attrs
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ice40/pack: Copy attributes to packed cell
2019-01-21 11:10:38 +00:00
b274a8f8f0
ice40/pack: Copy attributes to packed RAM cells
...
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-01-19 15:49:21 +01:00
830d462f92
ice40: Add error message if a selected site is not Global Buffer capable
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... rather than assert()-out during the call to getWireBelPins() call
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-01-18 17:53:24 +01:00
7d8b729ff4
ice40: Add timing data for all IO modes
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-07 17:18:40 +00:00
4444a39fd4
ice40: Improve handling of unconstrained IO
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-26 16:00:19 +00:00
953a3ac552
ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-20 20:52:54 +00:00
75335d4e1a
ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-20 18:50:34 +00:00
51155ec6a7
ci: Add attosoc smoketest for ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-12-08 17:09:27 +00:00
d790d0bb91
Merge pull request #163 from daveshah1/timing_opt
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Adding criticality calculation and experimental timing optimisation pass
2018-12-07 21:19:41 +00:00
144363693d
ice40: Report error for unsupported PLL FEEDBACK_PATH values
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:29:33 +00:00
e7fc42ac84
ice40: Improve bitstream error handling
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Fixes #161 and provides a clearer error for #170
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:19:48 +00:00
b732e42fa3
timing_opt: Reduce iterations to 30, tidy up logging
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 11:00:16 +00:00
f53dc8d3c9
timing_opt: Improve heuristics
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
f3adf5a576
timing_opt: Make an optional pass controlled by command line
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
254c5ea359
clangformat
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
b51308708b
timing_opt: Debugging and integration
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:53:01 +00:00
88e1e6bdf4
clangformat
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:52:46 +00:00
dbaabae235
ice40: Put debug logging behind ctx->debug
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 10:51:17 +00:00
d298687dc2
ice40: Fix carry chain splitting
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-05 10:12:23 +00:00
51cda136b1
ice40: Don't split carry chain in simple feed-out cases
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-04 12:31:32 +00:00
0c93b55650
ice40: Include I3 connectivity in chain
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Thanks @smunaut
Signed-off-by: David Shah <dave@ds0.me>
2018-12-04 12:02:26 +00:00
7fad6058bd
ice40: add reset global promotion threshold.
2018-12-04 07:40:55 +00:00
d4b3c1d819
ice40: Add support for placing SB_LEDDA_IP block.
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Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
2018-12-01 22:27:04 -03:00
8af367ad0a
ice40: Add a warning for unconstrained IO
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-29 19:35:19 +00:00
4e05d09397
Improve reporting of unknown cell types
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-29 19:26:23 +00:00
fc08856537
Merge pull request #157 from whitequark/fanout-thresh
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ice40: raise CE global promotion threshold
2018-11-29 09:12:47 +00:00
db96b88d79
ice40: raise CE global promotion threshold.
2018-11-29 00:12:48 +00:00
a974124a7a
ice40: print fanout of nets promoted to globals.
2018-11-28 23:52:48 +00:00
0872b63b0b
Merge pull request #155 from smunaut/issue_151
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ice40: Update the way LVDS inputs are handled during bitstream generation
2018-11-28 16:20:36 +00:00
ba958d1792
ice40: Try to be helpful and suggest using PAD PLL instead of CORE
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:58 +01:00
a65b12e8d6
ice40: Revamp the whole PLL placement/validity check logic
...
We do a pre-pass on all the PLLs to place them before packing.
To place them:
- First pass with all the PADs PLLs since those can only fit at one
specific BEL depending on the input connection
- Second pass with all the dual outputs CORE PLLs. Those can go
anywhere where there is no conflicts with their A & B outputs and
used IO pins
- Third pass with the single output CORE PLLs. Those have the least
constrains.
During theses passes, we also check the validity of all their connections.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:43 +01:00
5f0f2b060b
ice40: Update the way LVDS inputs are handled during bitstream generation
...
* Instead of "patching" input_en, we completely separate config for
normal and LVDS pair.
- For normal pair, nothing changes
- For LVDS pairs, the IE/REN bits are always set as if the input buffer
are disabled. Then if input_en was set to 1 (i.e. the input is
actually for something), then we set the IoCtrl.LVDS bit.
- Also for LVDS, if input is used, pullups are forcibly disabled.
* When scanning for unused IOs, never process those part of a LVDS pair.
They will have been configured by the complement
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-28 16:04:23 +01:00
80f7ef4b4b
ice40: Finer-grained control of global promotion
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-27 19:06:55 +00:00
584e8c58a6
ice40: During global promotion, only promote if this will actually fit !
...
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
a79f0db749
ice40: Add helper to know which global network is driven by a SB_GB Bel
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
fe2fa0e3ed
ice40: Improve PCF error handling
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Fixes #147
Signed-off-by: David Shah <dave@ds0.me>
2018-11-26 09:34:28 +00:00
2c6a2c40e1
Merge branch 'master' of github.com:YosysHQ/nextpnr
2018-11-26 09:23:31 +00:00
2951e37b45
ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-24 17:49:26 +00:00
65a5d05952
python: Fixes to get net wires map working
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-22 13:42:20 +00:00
9c5f4fb885
ice40/pll: Fix typo when testing for global port output net
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-20 23:53:08 +01:00
e8556aff37
ice40: Add support for SB_RGBA_DRV
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
de8de6304f
ice40: Add global network output support for LFOSC/HFOSC
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
271cc7be11
ice40/pack: Add helper to constain cells that are unique in the FPGA
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
519d4e2af8
ice40: Add support for SB_GB_IO
...
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.
It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
d8e4c21d96
ice40: Add support for PLL global outputs via PADIN
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
bc9f2da470
ice40: Introduce the concept of forPadIn SB_GB
...
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.
When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.
This is also what gets used to set the extra bits during bitstream
generation.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
325d46e284
ice40/chipdb: Add wires to global network for all cells that can drive it
...
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
3f4dc7c80e
ice40: Add GlobalNetowkrInfo in the chip database
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
c219d8fe4d
ice40: Fix BEL validity check for PLL vs SB_IO
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
9483a95a4a
ice40: Improve the is_sb_pll40_XXX predicates collection
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- Add a test for dual output PLL variant
- Make them handle the packet version of the cell
This will become useful for various tests during PLL rework
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
f6d6022984
ice40: Fix PLLTYPE for SB_PLL40_2F_PAD
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
ad23caef33
ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
78f3c2c37d
ice40: Make PLL default FEEDBACK_MODE to SIMPLE
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
35e9ec7737
ice40: Minor fix in predicate checking for logic port
...
- is_sb_pll40 covers all the PLL types
- Use helper to test for gbuf
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
ac5d767d4f
ice40/pack: Stop looking for BEL when we have one during PLL placement
...
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
5fb3353557
ice40/pack: Allow PLL to be constrained via 'BEL' attributes
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
8c69a3bba3
ice40/pack: Make sure we don't use a LOCKED bel when placing PLL
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
b29165eeba
ice40/arch: Add helper to check if a BEL is LOCKED or not
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
70e1fe423f
ice40/chipdb: Fix LOCKED keyword support to include all packages
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 13:12:43 +01:00
42fbb110fc
ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 13:12:43 +01:00
e1e8d8cd14
ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-16 16:36:57 +01:00
01950a2349
ice40/bitstream: Convert to UNIX line endings
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-16 16:24:56 +01:00
9c52afcf5f
clangformat
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-16 13:25:51 +00:00
20aa0a0eed
ice40: Remove unnecessary RAM assertion
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Fixes #121
Signed-off-by: David Shah <dave@ds0.me>
2018-11-16 13:18:53 +00:00
c5ba77e06b
Merge remote-tracking branch 'origin/master' into timingapi
2018-11-13 13:47:37 -08:00
51a2894762
[ice40] getBudgetOverride() to use constrained Z not placed Z
2018-11-13 12:51:46 -08:00
2d39cde17b
Merge remote-tracking branch 'origin/master' into timingapi
2018-11-13 12:12:11 -08:00
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve
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Major rewrite of "router1"
2018-11-13 11:39:51 -08:00
710ea1b265
Mark getArchOptions as override in derived classes
2018-11-13 11:03:48 -02:00
06e0e1ffee
Various router1 fixes, Add BelId/WireId/PipId::operator<()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-13 05:05:56 +01:00
fc5e6bec9a
timing: Add support for clock constraints
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
07e265868b
archapi: Add getDelayFromNS to improve timing algorithm portability
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
e633aa09cc
timing: Fix handling of clock inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
9687f7d1da
Working on multi-clock analysis
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
Sylvain Munaut
David Shah
Marcin Kościelnicki
David Shah
Simon Schubert
Miodrag Milanović
Eddie Hung
whitequark
Daniel Serpell
Pedro Vanzella
Clifford Wolf