86699b42f6
Switch to potentially-sparse net users array
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This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-27 13:47:05 +00:00
ddb084e9a8
archapi: Use arbitrary rather than actual placement in predictDelay
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
1db3a87c62
Code formatting
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 14:59:09 +02:00
76f5874ffc
Brought back printout of critical path source file references, added clk-to-q, source and setup segment types
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 10:16:45 +02:00
1ed692aca9
Shifted moving of data containers after printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 18:01:30 +02:00
9018782eaa
Added a commandline option controlled writeout of per-net timing details
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
6deff56e83
Moved timing result report storage to the context, added its writeout to the current utilization and fmax report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
c6dc1f535a
Added reporting critical paths in JSON format
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
d8571b6c00
Decoupled critical path report generation from its printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
12adbb81b1
Switched to JSON format for timing analysis report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
99ae5ef38e
Added writing a CSV report with timing analysis of each net branch
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
4730a4f339
timing: Always use max delay for required time
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-18 11:04:39 +01:00
287a860283
timing: Fix slack for unconstrained clocks
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-18 10:43:19 +01:00
f207068ee2
router2: Add experimental timing-driven ripup option
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-15 16:22:03 +01:00
4ac00af6fa
basectx: Add a field to store timing results
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-29 12:52:13 +01:00
14c676ab49
timing: Allow overriding of route delays
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-28 11:20:28 +01:00
76070a7647
timing: Fix out-of-bounds histogram bins in all cases
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-10 23:44:21 +01:00
889c295baf
sta: Fix a memory error introduced by the dict move
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-17 12:06:26 +01:00
2ffb081442
Fixing old emails and names in copyrights
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
b8a68f5f35
Using hashlib in timing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
579b98c596
Use hashlib for core netlist structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
ece10c3e04
timing: Fix domain init when loops are present
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-13 09:23:08 +01:00
8a4bf3a780
timing: Integration tweaks
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 10:04:35 +00:00
98d1c5a411
timing: Skip route delays for unplaced/nullptr cells
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 11:34:20 +00:00
1ff2023f32
timing: Replace all users of criticality with new engine
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 11:29:11 +00:00
ebc2527368
timing: Use new engine for HeAP
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
bbf5a7d461
timing: Add support for critical path printing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
e681e0f14c
timing: Slack and criticality computation
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
296e6d10c2
timing: Produce plausible Fmax figure
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
541376f8cc
timing: Add Fmax printing for debugging
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
16e7bba87b
timing: Add backwards path walking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
0528ceead1
timing: Add forward path walking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
9c8d1bd6e3
timing: Compute domain pairs
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
534e69fbff
timing: Add port-domain tracking
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
7a546b1554
timing: Add topological sort from Yosys
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
d0772ce1e3
timing: Import cell delays to our own structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 10:29:36 +00:00
c0a7cff304
Demote the 'no clocks' warning to info and make clearer
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-20 20:15:52 +00:00
7922b3bfc4
Replace DelayInfo with DelayPair/DelayQuad
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
535723f414
Start making use of getBelPinsForCellPin API
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This replaces getNetinfoSinkWire with 3 new functions for different use
cases.
At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:18:12 +00:00
9388df19d3
refactor: Replace getXName().c_str(ctx) with ctx->nameOfX
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This makes the ongoing migration to IdStringList easier.
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:14 +00:00
94e8847d67
cleanup: Spelling fixes
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Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 15:19:06 +00:00
6ecf7f86c8
cleanup: Remove dead/unused code
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Note that some '#if 0' code that might still be useful for debugging in
the future has been retained.
Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 14:59:13 +00:00
c30cadd19c
No longer need fstream include
2020-08-30 18:22:05 -04:00
cba4753c22
Only print filenames for now, default on
2020-08-30 18:19:41 -04:00
a8c110b045
Add option to print critical path source code
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In order to make debugging the critical path easier, add an option that
will log the location each net was defined, if known.
If the file that contains the definition is known, and is readable, also
print the part of the source HDL responsible for the signal definition.
2020-08-30 17:43:29 -04:00
109aa63474
clangformat
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Signed-off-by: David Shah <dave@ds0.me>
2020-08-20 09:46:49 +01:00
3611b7120c
timing: Fix counting of fanin in out-of-context mode
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Signed-off-by: David Shah <dave@ds0.me>
2020-08-12 10:42:26 +01:00
e6b85f1bc0
Fix embarassing use of topographical when meaning topological
2020-05-14 08:55:28 -07:00
564f40f6db
timing: Improve robustness to dangling/undriven logic
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-17 10:07:21 +00:00
f28186bb1b
timing: Fix critical path walking for ECP5
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-18 21:34:32 +00:00
gatecat
Maciej Kurc
D. Shah
Ross Schlaikjer
Eddie Hung