- experiment with notifyBelChange as an auxiliary cells reservation mechanism;
- since HCLK pips depend on the coordinates, and not on the tile type,
the tile type is copied if necessary;
- information about supported types of differential IO primitives has
been added to the extra information of the chip;
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add processing IO located on the sides of some chips. These are IOBUF,
which are converted into IBUF and OBUF not by fuses, but by signaling to
OE.
Also added the creation of a Global Set / Reset for all chips, instead
of a list of tile types, information from the apicula database is used,
and minor fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
To implement unusual IOs that have a dynamically changing configuration
it is convenient to store the switching method in the additional chip
data.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
a need to unify all wires included in the node at the stage of node
creation, when all wires have already been created.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- minor fixes for pinout saving;
- CST parser taken from generic-based apicula;
- $nextpnr IOB detachment is copied here because it is necessary to copy
attributes from deleted bels.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- RAM16SDP1, RAM16SDP2 and RAM16SDP4 support;
- Reading in these primitives is asynchronous, but we have taken
measures so that DFF Bels remain unoccupied and they can be used
to implement synchronous reading.
- misc fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Added support for ALU running in "2" ADDSUB mode, the mode that yosys generates for gowin;
- Supports specifying an arbitrary input carry as well as passing the output carry to logic;
- A small restructuring of the source files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
YRabbit