luke
/
nextpnr
mirror of https://github.com/YosysHQ/nextpnr.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,766 Commits 30 Branches 9 Tags 27 MiB
Commit Graph

1766 Commits

Author SHA1 Message Date
Sylvain Munaut 822b525035 placer1: During initial placement, don't rip-up strongly binded cells 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah 024db62ef0 Update README.md 
Fixes #74

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:47:16 +00:00
David Shah fe670cf3f6 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:37:39 +00:00
David Shah bbeab72ad9
Merge pull request #143 from daveshah1/ecp5_muxes 
ecp5: Adding support for LUT extension muxes up to LUT7
 2018-11-26 09:37:18 +00:00
David Shah 22ac41d627
Merge pull request #138 from YosysHQ/refactor_log 
Tidy up logging code, add log file support, make timing failures non-fatal errors
 2018-11-26 09:37:07 +00:00
David Shah 98858fe611
Merge pull request #139 from YosysHQ/fix_117 
router1: Fix unrouted, undriven nets
 2018-11-26 09:36:58 +00:00
David Shah eda77a5244 json: Remove superfluous floating node message 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:36:43 +00:00
David Shah fe2fa0e3ed ice40: Improve PCF error handling 
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:34:28 +00:00
David Shah 2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah b035cb9fcf Add nonfatal error support and use for timing failures 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:22:42 +00:00
David Shah ff978570b1
Merge pull request #146 from YosysHQ/fix_145 
ice40: Fix disconnection of PACKAGEPIN for PAD PLLs
 2018-11-24 18:00:45 +00:00
David Shah 2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
David Shah 8bda861a71
Merge pull request #144 from bgamari/patch-1 
docs/constraints: Fix typo
 2018-11-22 21:56:30 +00:00
Ben Gamari 7a61ffc3f4
docs/constraints: Fix typo 2018-11-22 16:55:46 -05:00
David Shah 65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
David Shah e48c9e73e7 python: Add wrapper for vectors to allow Python access to net.users 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 12:35:07 +00:00
David Shah 1731590160
Merge pull request #122 from YosysHQ/ecp5_timing 
ecp5: Use cell and pip timings from the Trellis database
 2018-11-22 11:55:25 +00:00
David Shah 48c793bd4d
Merge pull request #140 from xobs/readme-ubuntu-boost-list 
README: further specify required Boost packages for Ubuntu
 2018-11-22 08:52:30 +00:00
Sean Cross bfbea5bcb7 README: further specify required Boost packages for Ubuntu 
UWhen installing Boost, you can either install libboost-all-dev, or install
just the required packages.

Previously, `libboost-dev` was the only required package listed.

This adds `libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev
libboost-python-dev` to the list of required packages.

It addresses issue #128.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-11-22 14:06:24 +08:00
David Shah 8471d4249c router1: Fix unrouted, undriven nets 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:23:20 +00:00
David Shah 15d05296db
Merge pull request #134 from YosysHQ/issue129 
QUIET flag for cmake searches for boost python
 2018-11-21 17:17:45 +00:00
David Shah 51d1363dfe Change the log level of some timing-related messages 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:13:53 +00:00
David Shah b550791d92 Refactor log code and add log file support 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-21 17:08:45 +00:00
David Shah 01377d3f87
Merge pull request #135 from smunaut/ice40_typo 
ice40/pll: Fix typo when testing for global port output net
 2018-11-21 16:30:51 +00:00
Sylvain Munaut 9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Eddie Hung 35b3aaf18f QUIET flag for cmake searches for boost python 2018-11-20 10:41:24 -08:00
Serge Bazanski cf83d546f1
Merge pull request #133 from YosysHQ/yield_gui 
Add missing router1 ctx->yield() calls
 2018-11-20 19:31:29 +01:00
Clifford Wolf b5d518583e Add missing router1 ctx->yield() calls 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 18:58:15 +01:00
David Shah 343569105d
Merge pull request #131 from smunaut/ice40_fixes 
iCE40: Bug fixes and general improvement of global network support
 2018-11-20 10:11:32 +00:00
David Shah 0fb7735e45
Merge pull request #130 from smunaut/issue_127 
common/placer1: In random pick, only use grid if there is more than 64 BELs
 2018-11-20 10:11:21 +00:00
David Shah 04c5ed45bb
Merge pull request #132 from maikmerten/master 
add "randomize-seed" command-line option
 2018-11-20 10:11:09 +00:00
Maik Merten e167043e73 add "randomize-seed" command-line option 2018-11-19 19:45:12 +01:00
Sylvain Munaut d6fd0e7e5b common/placer1: In random pick, only use grid if there is more than 64 BELs 
If you have a large grid and very few BELs of a given type, picking a
random grid location yields very little odds of finding a BEL of that
type.

So for those, just put all of them at (0,0) and do a true random pick.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:52:40 +01:00
Sylvain Munaut e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 325d46e284 ice40/chipdb: Add wires to global network for all cells that can drive it 
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut c219d8fe4d ice40: Fix BEL validity check for PLL vs SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 9483a95a4a ice40: Improve the is_sb_pll40_XXX predicates collection 
- Add a test for dual output PLL variant
 - Make them handle the packet version of the cell

 This will become useful for various tests during PLL rework

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut f6d6022984 ice40: Fix PLLTYPE for SB_PLL40_2F_PAD 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 78f3c2c37d ice40: Make PLL default FEEDBACK_MODE to SIMPLE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00