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176 Commits

Author SHA1 Message Date
Alessandro Comodi 45618faf36 interchange: site router: fix log messages 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-10 14:20:54 +02:00
Alessandro Comodi beff2b912c interchange: site router: fix illegal site thru paths 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-10 14:05:46 +02:00
gatecat 9a1cad85fe interchange: Adding a basic global buffer placer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:28:59 +01:00
gatecat 9b3fb00908 interchange: Initial global routing implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:28:56 +01:00
gatecat b8c8200683 interchange: Add more global cell info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-07 10:25:18 +01:00
gatecat 0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
gatecat 49caad0b7b interchange/nexus: Add counter example 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 14:15:37 +01:00
gatecat dcb09ec8de interchange: Implement getWireType 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:31 +01:00
gatecat ecf24201ec interchange: Add wire types to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-30 11:07:14 +01:00
gatecat 3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword 
interchange: allow LOC keyword in XDC files
 2021-04-20 14:12:14 +01:00
Jan Kowalewski d1548ed317 interchange: allow LOC keyword in XDC files 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-04-20 14:35:15 +02:00
gatecat 18459a9e4c interchange: Handle disconnected/missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:46:35 +01:00
gatecat 872b3aa63d interchange: Add default cell connections to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-19 10:16:26 +01:00
gatecat d4aac6586c Add Python bindings for placement tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-15 10:00:45 +01:00
gatecat 8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation 
interchange: add FASM generation target and clean-up tests
 2021-04-14 14:28:01 +01:00
Alessandro Comodi dfc9c3df8c interchange: add FASM generation target and clean-up tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-14 14:36:07 +02:00
gatecat 4e346ecfba Hash table refactoring 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:19 +01:00
gatecat 06e54f08e6 interchange: Allow pseudo-cells with no input pins 
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-13 10:58:41 +01:00
gatecat fc15105643 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-12 10:26:39 +01:00
gatecat 93e34b8754 interchange: Disambiguate cell and bel pins when creating Vcc ties 
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.

This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 10:26:32 +01:00
Keith Rothman ae2f7551c1 [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman 3200026e1f [interchange] Remove requirement to have wire_lut. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman c2a6f6ce62 [interchange] Fix invalid use of local variables due to refactoring. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman 8773c645ca [interchange] Prevent site router from generating incorrect LUTs. 
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal.  This case is now prevented by tying the
output of the LUT to an unused net.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman c11ad31393 [interchange] Scale edge cost of pseudo pips. 
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman 9b82ded77b [interchange] Fix missing inline methods in site_arch.impl.h 
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman 90aa1d3b7e [interchange] Disallow site edges during general routing. 
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
Keith Rothman 0d41fff3a7 [interchange] Add crude pseudo pip model. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-06 10:42:05 -07:00
gatecat ff449ca997
Merge pull request #661 from litghost/document_site_router 
[interchange] Add some documentation for the site router.
 2021-04-06 09:20:03 +01:00
gatecat 8e0d8df791
Merge pull request #657 from acomodi/interchange-counter-multi-board 
interchange: counter: testing on multiple boards
 2021-04-06 08:12:02 +01:00
Keith Rothman 4301e4705b [interchange] Add some documentation for the site router. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-05 15:15:48 -07:00
Keith Rothman 009d3b64b6 [interchange] Update to v6 of FPGA interchange chipdb. 
Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:24:06 -07:00
Alessandro Comodi 366f8782cb interchange: counter: testing on multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-04-01 10:23:07 +02:00
gatecat ec98fee1ee
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake 
fpga_interchange: Add CMake support for Nexus/prjoxide
 2021-03-31 15:14:51 +01:00
gatecat 3678eff5dc interchange: Fix nexus cmake review comments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-31 10:11:09 +01:00
Keith Rothman 8675945b26 Fix bug where DedicateInterconnect incorrectly allows some placement. 
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 13:24:39 -07:00
Keith Rothman 7e47af1085 [interchange] Fix site pip check for drivers. 
Previous code allowed router to entire sites with no sinks.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-30 10:04:18 -07:00
gatecat a003aae7c2 interchange: Split xc7 and nexus chipdb cmake 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat ecfaae7f9e interchange: Add Nexus LUT test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat b6b8959397 interchange: Add Nexus to CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat 3cb5e81d50 interchange: Add CMake support for Nexus/prjoxide 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
gatecat 8863b962fd interchange: Fix illegal placements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 15:28:19 +01:00
gatecat 692d7dc26d
Merge pull request #645 from litghost/add_counter_and_ram 
FPGA interchange: Add counter and ram tests
 2021-03-29 18:23:16 +01:00
Alessandro Comodi b5ba3ee9ee interchange: add archcheck tests to all-device-test target 
This increases parallelism and should make the FPGA interchange CI
faster

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
Keith Rothman f33d02dca9 Update README with latest develpment progress. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:15 -07:00
Keith Rothman 55c9d43c70 interchange: Fix bug in site router where a bad solution isn't remove. 
This resulted in valid site routing solutions being missed.  Underlying
bug was an off-by-one error when unwinding a failed solution.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:14 -07:00
Keith Rothman c8dccd3e7b Implement debugging tools for site router. 
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
 - Adds "explain_bel_status", which should be an exhaustive diagnostic
   of the status of a BEL placement.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:56:11 -07:00
Keith Rothman cc4f2b4516 Add some FIXME's around VCC assumption in LUT logic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman bbe1881293 Add targets to generate YAML outputs for DeviceResource files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00
Keith Rothman 91ca5f110b Re-work LUT mapping logic to only put VCC pins when required. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-25 17:20:13 -07:00