Commit Graph

684 Commits

Author SHA1 Message Date
gatecat 8d063d38b1 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-12 07:59:36 +01:00
gatecat eac864ebdc ecp5: Bind write_bitstream to Python
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-09 20:05:20 +01:00
gatecat a35c80cc10 ecp5: Tweak delay prediction
Signed-off-by: gatecat <gatecat@ds0.me>
2022-04-20 11:29:08 +01:00
gatecat efb58711b0 ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels 2022-04-07 18:02:36 +01:00
gatecat 2635bab2f1 ecp5: Fix double-counting of FFs in report
Signed-off-by: gatecat <gatecat@ds0.me>
2022-03-16 15:44:45 +00:00
Maya 9f53bd4278 ecp5: accept lowercase characters in hex strings. 2022-03-11 23:34:45 +00:00
Maya 2a3d0c1d29 ecp5: verify hex strings contain only valid characters. 2022-03-11 23:31:23 +00:00
gatecat 0a70b9c992
Merge pull request #925 from YosysHQ/gatecat/netlist-iv
Switch to potentially-sparse net users array
2022-03-01 16:38:48 +00:00
gatecat 9b3e687eda ecp5: Fix PDPW16K clock param renaming
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-28 13:10:00 +00:00
gatecat 86699b42f6 Switch to potentially-sparse net users array
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-27 13:47:05 +00:00
gatecat 6a32aca4ac refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-18 11:13:18 +00:00
gatecat 76683a1e3c refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 17:09:54 +00:00
gatecat 9ef0bc3d3a refactor: Use cell member functions to add ports
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 16:45:45 +00:00
gatecat 30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
gatecat f36188f2e1 ecp5: LUT permutation support
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-13 20:22:06 +00:00
Matt Johnston 90b0e90bbe ecp5: Reduce some chipdb fields sizes
This reduces the final binary size by ~7 MB for 85k
2021-12-13 11:48:50 +08:00
gatecat a933f82845 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-12 18:49:37 +00:00
Matt Johnston 80dd442412 ecp5: Use a vector rather than dict
This improves router1 performance vs the default dict
Using it for wire2net, pip2net, wire_fanout
2021-12-12 22:09:11 +08:00
gatecat ce030a474c ecp5: Fix packing of IOFF with IODELAYs
Signed-off-by: gatecat <gatecat@ds0.me>
2021-11-05 15:16:43 +00:00
YRabbit ddc368f0dd Fix mistype.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-09-29 14:21:06 +10:00
gatecat e15f0db408 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-24 12:48:08 +01:00
gatecat 897a2fccb6
Merge pull request #798 from kleinai/extref-loc
Make EXTREFB handling more robust
2021-08-19 16:36:18 +01:00
Aidan Klein e6006805ce Make EXTREFB handling more robust
Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA.
Also adds location constraints specifically for EXTREFB.
2021-08-18 20:49:55 -04:00
gatecat a66cd0200b clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-14 20:22:54 +01:00
Greg Davill 200c57f475 ecp5: Enable OPENDRAIN on differential outputs 2021-08-14 19:26:58 +09:30
gatecat 5482b9a0c6 ecp5: Copy REGMODE in PDP mode to both A and B ports
Signed-off-by: gatecat <gatecat@ds0.me>
2021-08-02 20:58:45 +01:00
gatecat 81c549549d ecp5: Add DCSC support
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 11:45:37 +01:00
gatecat 2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat e9d5b75d1d ecp5: Add missing clock edge assignments
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-10 13:10:29 +01:00
gatecat 8fa3088057 ecp5: Don't attempt to promote undriven nets to globals
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-07 21:20:40 +01:00
gatecat dcbb322447 Remove redundant code after hashlib move
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
gatecat eca1a4cee4 Use hashlib in most remaining code
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
gatecat ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
gatecat 43b8dde923 Use hashlib in placers
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:04:49 +01:00
gatecat 579b98c596 Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
gatecat ff72454f83 Add hash() member functions
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
gatecat c82df9e40d ecp5: Use new cluster API
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:59:58 +01:00
gatecat 4bdf4582f0 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 18:38:30 +01:00
Adam Greig d3a6cf3ae7
Only set CIBOUT_BYP on MULTs that are not feeding an ALU. 2021-04-29 02:23:45 +01:00
Adam Greig b6c608e038
Add check_alu to Ecp5Packer
Checks that every ALU54B is correctly connected to two MULT18X18Ds:

* SIGNEDIA and SIGNEDIB connected to SIGNEDP
* MA and MB connected to P
* A and B connected to {ROA, ROB}

Diamond enforces these requirements; the connections are fixed
in any event so no other connection is possible.
2021-04-29 02:23:44 +01:00
Adam Greig d4c688297c
Add relative constraints to position MULT18X18D near connected ALU54B. 2021-04-29 02:23:43 +01:00
Adam Greig 9538954cc6
Add ALU54B.REG_OPCODEOP1_1_CLK parameter support 2021-04-29 02:23:42 +01:00
Keith Rothman fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat 1ff2023f32 timing: Replace all users of criticality with new engine
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-04 11:29:11 +00:00
gatecat 23413a4d12 Fix compiler warnings introduced by -Wextra
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
gatecat 7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
Keith Rothman 99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
gatecat 11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00