* Check SER_CLK more
* Use connectPorts
* move rewire code
* Move data structures
* move placement decision for later
* cleanups
* find working layout
* clangformat
* Inverted input on ODDR
* Fix some tests
* Copy clocks for multi die
* cleanup
* reporting
* bugfix
* handle PLL special inputs
* Fix user globals
* Proper DDR per bank and cleanup
* Add extra data for die regions and create them
* Better forced_die implementation
* Copy region to newly generated cells, and update when constrained
* Update PLL error messages
* Add TODO comment
* Add bridge support
* Use bridge only if CPE is unused
* do not use CPE_MULT for MUX routing
* Fixed and documented
* delay for CPE_BRIDGE
* Convert bridge pips into bels
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
* recursively reassign bridges
* reconnect cell ports to new nets
* handle inversion bits
* sort data in output for easier compare
* one to be removed after testing
* debug message
* Remove need for notifyPipChange
* use same logic for detecting bridge pips
* make sure that the pip used is the one assigned
* one wire may feed multiple ports
* remove #if
* clean up wire binding
* add debugging
* fix
* clangformat
* put back to error
* use tile instead of getting name out of bel/pip
* bump chipdb
* adressing review comments
* Addressed last one
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* CPE mapping improvements
* Use CP_OUT for adders
* Fixes
* Small fixes
* Cleanups
* Cleanup
* Cleanups
* Fixes
* Fixes
* Optimize
* Cleanup
* clangformat
* Cleanup
* Cleanup
* Bump required version of database
* Cleanup
* Resolve name conflicts
* Fix signal routing
* Make CPE_LATCH separate
* Add more timings models, need updated values
* Fixed warning
* multiplier support from lofty/gatemate-mult
* explicitly zero some params in B passthrough
* comment the relevant CPE inputs in check_multipliers
* Rename some of bels
* remove _lower from name
* refactor multiplier checking
* Revert "remove _lower from name"
This reverts commit daa1041bdf.
* Fixe net name to be unique
* Make sure we at least generate bitstream with all info
* Simplify zero
* Bounded cell type in gui
* typo fix
* Remove A passthrough inversion option
* Clean up CarryGenCell config
* Update a passthru to use new primitives
* Cleanup for adders
* Clean up MsbRoutingCell
* Cleanup
* Refactor A connection code
* Make it more as in PR #1513
* Added cplines to bpassthru and fixed constant driver for A
* Add parts
* Added comp out connections
* clangformat
* clangformat
* Clean up B passthrough connections
* wire up a bunch of intermediate signals
* Bit of cleanup
* handing of C_EN_IN
* C_EN_CIN fixes
* connect f_route to its lines
* fix cite for FRoutingCell
* fixup, oops
* connect multfab to its lines
* Commented line
* Connect CPOUTs
* Handle C_I params
* connect CINY1 for CarryGenCell
* fix carry gen CINX
* Update L2T4 model
* Updates for ADDCIN
* clangformat
* fix some issues with multfab and f_route
* look at C_I when doing inversion
* Only set some C_I signals when used
* Fix one more place
* do not use cplines so we can merge in one cell
* Cover cases that could be optimized out
* clangformat
* Cleanups
* Disable multiplier usage for now
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Miodrag Milanović
Lofty