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nextpnr
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62 Commits

Author SHA1 Message Date
Eddie Hung aa7f7d6a97 clangformat 2018-11-03 15:18:26 -07:00
Eddie Hung d80b63cc55 [xc7] Re-enable PCF reading 2018-11-03 15:17:53 -07:00
Eddie Hung 4239e3668a [xc7] Make clg400 the default package (Zybo) 2018-11-03 15:02:09 -07:00
Eddie Hung c6bf8aff43 [xc7] Fix timing analysis for constant drivers 2018-11-03 14:24:29 -07:00
Eddie Hung 8f1c91151b Revert "[xc7] Fix getPortTimingClass for IOBs" 
This reverts commit 5d9019994e.
 2018-11-03 13:30:58 -07:00
Eddie Hung 0e1c23a07b [xc7] blinky.v to only have 4 LEDs 2018-11-03 13:27:39 -07:00
Eddie Hung 5d9019994e [xc7] Fix getPortTimingClass for IOBs 2018-11-03 12:55:36 -07:00
Eddie Hung 324ff41f13 Fix Torc path 2018-11-03 12:10:21 -07:00
Eddie Hung 735c7c7c9c torc now expected to be /opt/torc 2018-11-03 11:41:36 -07:00
Eddie Hung 834f5f58c2 Fix wire delays, disable BUFG I->O routethrough 2018-09-05 22:24:46 -07:00
Eddie Hung 5214d1dbb5 Segment anchors may not be beginning of wires 2018-09-04 11:05:03 -07:00
Eddie Hung d0916943c5 Extend delays to cover BYP and FAN 2018-09-04 10:41:32 -07:00
Eddie Hung c7f0bdfc1b Move DelayInfo into loop 2018-09-04 10:35:12 -07:00
Eddie Hung db6e81d6c3 Populate Arch::getWireDelay() 2018-09-04 10:11:10 -07:00
Eddie Hung 7da5e2b525 Reduce predictDelay/estimateDelay to 100ps per tile 2018-09-04 10:10:27 -07:00
Eddie Hung d78f5a1d5b Build a pip_to_dst_wire lookup to speedup routing 2018-09-03 22:59:34 -07:00
Eddie Hung 30fe1f229a Set CE0INV and S0INV for BUFGCTRL; PRESELECT_I0 to be TRUE if not set 2018-09-03 22:25:05 -07:00
Eddie Hung 2eeb59d9f1 Re-enable routing 2018-09-03 22:24:59 -07:00
Eddie Hung 3a5665c1cb Speedup placement slightly using bel_to_loc 2018-09-03 21:00:11 -07:00
Eddie Hung 4f61d2dae7 Add yosys script 2018-09-03 19:23:36 -07:00
Eddie Hung 86fa032b63 picorv32_top to instantiate BUFGCTRL, and picorv32.sh to use picorv32.ys script 2018-09-03 19:23:00 -07:00
Eddie Hung 7f1c1ecaf0 blinky.v to instantiate BUFGCTRL correctly 2018-09-03 19:22:39 -07:00
Eddie Hung bf5a4717f5 Add pips to XDL output 2018-09-03 13:40:52 -07:00
Eddie Hung 6d17810dde Merge fixes 2018-09-03 13:20:19 -07:00
Eddie Hung c128df127b Do not consider route-through for CLB tiles 2018-09-03 13:17:16 -07:00
Eddie Hung d2597bcd8d Fix segments 2018-09-03 00:10:16 -07:00
Eddie Hung 3f865f9049 Fix Arch::estimateDelay() 2018-09-02 23:38:53 -07:00
Eddie Hung 7e693ff27d Precompute pips too 2018-09-02 19:06:20 -07:00
Eddie Hung ca7eef26ac Wires now encapsulate segments 2018-09-02 16:57:11 -07:00
Eddie Hung df2f295545 Apparently netgen needs SYNC_ATTR to be set 2018-09-02 13:09:28 -07:00
Eddie Hung 82fbc551f8 Fix DRC errors 2018-08-21 22:58:20 -07:00
Eddie Hung 3a177c72c6 Preserve packed LUT name as LUT_NAME parameter 2018-08-21 22:24:14 -07:00
Eddie Hung b658a39d73 IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky 2018-08-21 22:18:00 -07:00
Eddie Hung 5b6255abf1 Fix LUT masks, add speedgrade, fix IOB type 2018-08-20 21:50:06 -07:00
Eddie Hung 0a16e24c82 create_ice_cell -> create_xc7_cell 2018-08-20 19:29:04 -07:00
Eddie Hung 3e1085ecb5 Combine IOB33S and IOB33M 2018-08-20 19:25:54 -07:00
Eddie Hung f7be783a32 Escape flop names as well 2018-08-20 19:21:53 -07:00
Eddie Hung 718f5b81f0 Escape colons in config names 2018-08-20 19:19:45 -07:00
Eddie Hung 699bd3ef5a Fix for leading '+', and use An for LUT masks 2018-08-19 22:31:50 -07:00
Eddie Hung a87f26b254 Update comment 2018-08-19 19:41:24 -07:00
Eddie Hung dcc08b27cc Output unrouted nets into XDL 2018-08-19 19:41:11 -07:00
Eddie Hung 07fb4702ce Populate LUT masks 2018-08-19 19:16:24 -07:00
Eddie Hung a7ccc01c45 Use getBelType() 2018-08-19 17:38:55 -07:00
Eddie Hung 17918b5992 Fix for multiple id_SLICE_LUT6 per actual SLICE 2018-08-17 23:05:12 -07:00
Eddie Hung d05ac75fda Add basics for XDL exporter 2018-08-17 21:52:34 -07:00
Eddie Hung b8b9813056 id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation() 2018-08-14 08:42:27 -07:00
Eddie Hung 72c785db0e Convert to use torc_info 2018-08-12 22:09:16 -07:00
Eddie Hung 7b15569c69 Use general pin names for QUARTER_SLICE 2018-08-12 20:29:04 -07:00
Eddie Hung 56b7299cca {SLICEL,SLICEM} -> QUARTER_SLICE 2018-08-12 20:21:03 -07:00
Eddie Hung f6f20dce0c Rename ddb to torc 2018-08-12 19:20:13 -07:00