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61 Commits

Author SHA1 Message Date
gatecat 7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
gatecat c60fb94b6c refactor: Use IdString::in instead of || chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 18:58:22 +01:00
gatecat 77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
Maciej Dudek 8c4e3e91cc Change write_dcc to work with tilegroups from prjoxide 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-05-27 10:58:39 +02:00
gatecat 2ed68a21db clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-31 10:49:00 +01:00
Maciej Dudek b9e76d1bcd Rename parse_lattice_param to parse_lattice_param_from_cell 
Add new definition for parse_lattice_param

Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-30 14:59:47 +02:00
Maciej Dudek 49cc4ca30b Nexus: Fixed OSCA parameters, add pll default parameters 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-18 17:26:06 +01:00
Maciej Kurc 43861c0ee2 nexus: Added support for the DCS Bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-16 09:20:15 +01:00
Maciej Kurc 1cc71c7846 nexus: Added FASM feature emission for DCC and port timing class info 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-15 10:43:31 +01:00
gatecat 6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
Karol Gugala 500fa6f442 nexus: handle SLEWRATE in pdc 2021-12-20 15:09:03 +01:00
gatecat 502fcff765 nexus: LUT permutation support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 15:26:16 +01:00
gatecat f395ad3e27 nexus: Support for split Vcc routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 15:00:59 +01:00
Maciej Kurc 8ffd30cb2d Use correct names for IDDRX1_ODDRX1 FASM features 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 15:52:56 +02:00
Maciej Kurc ef9eee6b15 Added automatic inference and integration of FFs driving T pin into IOLOGIC 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
gatecat 5686fdcf1c nexus: Basic packer and FASM support for I/ODDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 13:27:02 +01:00
gatecat 3d528adfdc nexus: Disable center DCC-thrus on 17k device 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:52:10 +01:00
gatecat 84fc2877c6 nexus: Fix FASM gen for DCC-thru 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 13:23:42 +01:00
gatecat 2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat 13c037cc08 nexus: Fix LRAM x coord 2021-06-10 10:10:26 +01:00
gatecat ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat 579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat 99298d0aba nexus: Fix some IO FASM gen 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 12:04:01 +01:00
gatecat 7ae3f636ef nexus: Fix LIFCL-17 LRAM FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 11:56:07 +01:00
gatecat a6a92f6b6b nexus: Fix default IO config 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:35:44 +01:00
gatecat 0b1e089547
Merge pull request #651 from YosysHQ/gatecat/nexus-vcco 
nexus: Fix bank Vcco FASM
 2021-03-29 21:32:35 +01:00
gatecat df339f4f3c nexus: Default HF_OSC_EN to ENABLED 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 21:25:14 +01:00
gatecat d2579282a6 nexus: Fix bank Vcco FASM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-29 20:38:50 +01:00
gatecat 0f425aff5a nexus: Fix FASM gen for LIFCL-17 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-26 13:06:03 +00:00
Keith Rothman fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
gatecat 08c7f97b1e nexus: Support for hard DPHY 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:59:18 +00:00
Keith Rothman c99fbde0eb Mark IdString and IdStringList single argument constructors explicit. 
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:07 -08:00
D. Shah b87ab0ee9d Make RelSlice uncopyable 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 20:49:14 +00:00
D. Shah e049d5f2fc nexus: Switch from RelPtr to RelSlice 
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 17:24:01 +00:00
David Shah f923d32620 nexus: Add support for initialised LRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 11:57:10 +00:00
David Shah 270efdca85 nexus: Add basic LRAM support (no init) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:07:34 +00:00
David Shah 86e6a2225c nexus: Add PLL support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 15:01:46 +00:00
David Shah 54539b8519 nexus: Larger DSP tweaks 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah 9203181625 nexus: Support for unclocked 9x9 multiplies 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah e6c2887773 nexus: Basic support for carries 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah f8dca82a71 nexus: Basic support for differential IO types 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah e8e6316f88 nexus: EBR fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah 27ecaf3e88 nexus: EBR FASM generation 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah cbf99d5e53 nexus: LUTRAM support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah c80144b7f0 nexus: Generate FASM files that can be used standalone 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah da1e3c8612 nexus: Add constant/inversion packing 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah 1bb509897c nexus: More pin styles and FASM pinmux gen 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah 0eb5c72cc5 nexus: Refactor cell pin style db 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah 7f03f4d896 nexus: Tidy up FASM backend 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00
David Shah af3af59df4 nexus: Use tilegroups for IO bitgen 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:27 +00:00