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34 Commits

Author SHA1 Message Date
Lofty 0492c55efd
ci: test that BUILD_RUST=ON builds (#1459) 2025-03-03 14:44:33 +01:00
gatecat 0c458f14f2 generic: Enable viaduct example test in CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-02-25 15:28:46 +00:00
YRabbit f3a5024de2
Gowin: Remove nextpnr-gowin (#1318) 
Boards with Gowin chips are supported in the Himbaechel architecture
with much greater correctness and a wider range of primitives.

In fact, at the moment the advice “use himbaechel-gowin” immediately
solves a
significant part of the issues opened by users.

Of course, you need to wait for amendments to oss-cad-suite, at least
https://github.com/YosysHQ/oss-cad-suite-build/pull/109

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-02-14 00:08:12 +00:00
Catherine cd7f7c12f1 CMake: refactor architecture-specific build system parts. 
Two user-visible changes were made:
* `-DUSE_RUST` is replaced with `-DBUILD_RUST`, by analogy with
  `-DBUILD_PYTHON`
* `-DCOVERAGE` was removed as it doesn't work with either modern GCC
  or Clang
 2025-01-21 17:13:03 +00:00
Catherine dcfb7d8c33 CMake: align Himbaechel targets with non-Himbaechel ones. 
Primarily, this commit makes both of them use the `BBAsm` functions
to build and compile `.bba` files.

In addition, Himbaechel targets are now aligned with the rest in
how they are configured: instead of having all uarches enabled with
all of the devices disabled (the opposite of the rest of nextpnr),
uarches must be enabled explicitly but they come with all devices
enabled (except for Xilinx, which does not have a list of devices).
 2025-01-21 17:13:03 +00:00
gatecat fcdaf3f86c Remove fpga_interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 13:10:30 +02:00
Miodrag Milanovic 9bb46b98b4 update ci build script 2024-04-05 12:25:52 +02:00
gatecat 565927dfcc himbaechel: Add discovery of uarch and chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-15 08:23:43 +02:00
gatecat 57b923a603 himbächel: Initial implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-13 08:26:41 +02:00
Miodrag Milanovic 0067bcc615 use latest trellis and add arch tests 2023-05-04 14:23:08 +02:00
gatecat 92a58a2631 ci: Restructure and move entirely to GH actions from Cirrus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 18:42:39 +01:00
gatecat 29654c52be ci: Fixes for latest RapidWright 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-17 20:01:44 +00:00
gatecat d89afc2aa6 ci: Enable -Werror for interchange arch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-28 09:42:25 +01:00
Alessandro Comodi 721e760f1a ci: remove RapidWright patching 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-24 08:23:59 +02:00
Alessandro Comodi aa1784c5d9 interchange: ci: add RW patch for missing cell bel maps 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-11 11:49:59 +02:00
gatecat bcc5158eab ci: Bump mistral version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-05 13:01:49 +01:00
gatecat dcbb322447 Remove redundant code after hashlib move 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:20 +01:00
gatecat 0426ba4e87 interchange: Add LIFCL-40 EVN tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-01 09:52:40 +01:00
gatecat 6cef569155 ci: Use GH only for Mistral and fpga-interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 15:53:25 +01:00
gatecat b0f57d234f ci: Re-enable abseil for interchange CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-14 10:30:53 +01:00
gatecat 7acef00443 interchange: Pin prjoxide commit 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-04-09 11:17:25 +01:00
Keith Rothman 3a85088d66 [interchange] Update interchange CI for new chipdb change. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-04-01 15:59:48 -07:00
gatecat 3678eff5dc interchange: Fix nexus cmake review comments 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-31 10:11:09 +01:00
gatecat 9259763599 ci: Build prjoxide only for LIFCL 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:55:03 +01:00
gatecat b6b8959397 interchange: Add Nexus to CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-30 16:31:51 +01:00
Alessandro Comodi d0bc033ab8 gh-actions: better yosys caching based on version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 15:11:03 +01:00
Alessandro Comodi c4cb86efe9 gh-actions: use ccache and build tools before running tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-25 16:24:52 +01:00
Alessandro Comodi 9f28fa4e75 gh-actions: interchange: multiple jobs, one for each device 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-24 15:37:03 +01:00
Keith Rothman 720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:41:45 -07:00
Keith Rothman 8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
Keith Rothman 694f9ec3a5 Increment required python-fpga-interchange version. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:33:12 +00:00
Alessandro Comodi f9e9fadbc8 github-actions: use capnp v0.8.0 
This also updates the note in the README for the FPGA interchange

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 16:57:07 +01:00
Alessandro Comodi 83544cdf6a github-actions: pin python-fpga-interchange to tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 16:34:27 +01:00
Alessandro Comodi c68dfb09c4 github-actions: add basic CI to test FPGA interchange 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00