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4,772 Commits 30 Branches 9 Tags 27 MiB
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21 Commits

Author SHA1 Message Date
gatecat 9b51c6e337 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 14:51:33 +02:00
Rowan Goemans 098dcaedec timing: remove the articial clock delay inflation 2024-09-24 08:57:21 +02:00
Rowan Goemans 0fce4b8f4e timing: lower clock_delay_fact to 1 to check if CI passes 2024-09-24 08:57:21 +02:00
Rowan Goemans 25d64b2105 timing_log: Fix logging indendation to match master 
timing: Disable clock_skew analysis by default
 2024-09-24 08:57:21 +02:00
Rowan Goemans bca6f6394a timing: Fix slack calculations 
timing: Fix max_delay_by_domain_pair function
timing: Fix hold time check
 2024-09-24 08:57:21 +02:00
Rowan Goemans 86106cb49a timing: integrate c2c delays and cleanup code 2024-09-24 08:57:21 +02:00
Rowan Goemans fc3b2de8da timing: Add clock skew to arrival and required time 2024-09-24 08:57:21 +02:00
Rowan Goemans 82ea65d984 timing: Report min delay violated in timing logger 2024-09-24 08:57:21 +02:00
Rowan Goemans c25da06d03 timing: Start identification of min_delay violations 2024-09-24 08:57:21 +02:00
Rowan Goemans 44665a9c4d timing: Allow critical path traversal for shortest paths 2024-09-24 08:57:21 +02:00
Rowan Goemans 8d0f52fbf9
timing: Move towards DelayPairs for timing reporting (#1359) 2024-09-11 07:23:46 +01:00
rowanG077 38d2a4b844 tmg: Fix argument order in run method 
Router 2 expects "update_route_delays" to be the first argument to `tmg.run`.
 2023-09-25 13:20:40 +02:00
rowanG077 240f89081f Add back error/warning for combinational loops 2023-08-18 09:15:37 +02:00
rowanG077 d2a489d5e9 Remove old timing analyser 2023-08-18 09:15:37 +02:00
rowanG077 596873c302 tmg: Add net_timings, crit path and slack hist 2023-08-18 09:15:37 +02:00
rowanG077 8b51674a6b Add critical path report to modern timing engine 2023-08-18 09:15:37 +02:00
rowanG077 914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
Rowan Goemans 5b958c4d80
Analyse async paths in TimingAnalyser (#1171) 2023-06-09 08:01:47 +02:00
Maciej Kurc 9000c41c4b Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-09-20 14:40:40 +02:00
Maciej Kurc 9a61ad9234 Augmented TimingAnalyser class with detection of clock to clock relations 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-08-30 17:30:58 +02:00
gatecat 49f178ed94 Split up common into kernel,place,route 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-04-08 13:42:54 +01:00